AT89LP6440-20AU Atmel, AT89LP6440-20AU Datasheet - Page 82

• Manufacturer Part Number: AT89LP6440-20AU
• Description: MCU 8051 64K FLASH ISP 44TQFP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP6440-20AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: 8051
• Family Name: 89LP
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 38
• Interface Type: 2-Wire/SPI
• On-chip Dac: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15. General-purpose Interrupts
Figure 15-1. GPI Block Diagram
82
AT89LP6440 - Preliminary
(P1.7) GPI7
(P1.6) GPI6
(P1.5) GPI5
(P1.4) GPI4
(P1.3) GPI3
(P1.2) GPI2
(P1.1) GPI1
(P1.0) GPI0
another interrupt will be generated. Both INT0 and INT1 may wake up the device from the
Power-down state.
The General-purpose Interrupt (GPI) function provides 8 configurable external interrupts on
Port 1. Each port pin can detect high/low levels or positive/negative edges. The GPIEN register
select which bits of Port 1 are enabled to generate an interrupt. The GPMOD and GPLS regis-
ters determine the mode for each individual pin. GPMOD selects between level-sensitive and
edge-triggered mode. GPLS selects between high/low in level mode and positive/negative in
edge mode. A block diagram is shown in
clock cycle. In level-sensitive mode, a valid level must appear in two successive samples before
generating the interrupt. In edge-triggered mode, a transition will be detected if the value
changes from one sample to the next. When an interrupt condition on a pin is detected, and that
pin is enabled, the appropriate flag in the GPIF register is set. The flags in GPIF must be cleared
by software. Any GPI interrupt may wake up the device from the Power-down state.
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
GPLS
7
6
5
4
3
2
1
0
GPMOD
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
GPIEN
CLK
Figure
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
GPIF
15-1. The pins of Port 1 are sampled every
7
6
5
4
3
2
1
0
Interrupt
3706A–MICRO–9/09