AT89LP6440-20AU Atmel, AT89LP6440-20AU Datasheet - Page 25

• Manufacturer Part Number: AT89LP6440-20AU
• Description: MCU 8051 64K FLASH ISP 44TQFP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP6440-20AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: 8051
• Family Name: 89LP
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 38
• Interface Type: 2-Wire/SPI
• On-chip Dac: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5-1.
3706A–MICRO–9/09
Symbol
MRW
SMLB
SMLA
CBE1
CBE0
MVCD
DPRB
DSPR = E2H
Not Bit Addressable
Bit
1-0
Function
M Register Window. Selects which pair of bytes from the 5-byte M register is accessible through MACH (E5H) and
MACL (E4H) as shown in
order portion of the fractional result is discarded.
Signed Multiply Operand B. When SMLB = 0, the MUL AB instruction treats the contents of B as an unsigned value.
When SMLB = 1, the MUL AB instruction interprets the contents of B as a signed two’s complement value. SMLB does
not affect the MAC operation.
Signed Multiply Operand A. When SMLA = 0, the MUL AB instruction treats the contents of ACC as an unsigned value.
When SMLA = 1, the MUL AB instruction interprets the contents of ACC as a signed two’s complement value. SMLA
does not affect the MAC operation.
DPTR1 Circular Buffer Enable. Set CBE1 = 1 to configure DPTR1 for circular addressing over the two circular buffer
address ranges. Clear CBE1 for normal DPTR operation.
DPTR0 Circular Buffer Enable. Set CBE0 = 1 to configure DPTR0 for circular addressing over the two circular buffer
address ranges. Clear CBE0 for normal DPTR operation.
MOVC Index Disable. When MVCD = 0, the MOVC A, @A+DPTR instruction functions normally with indexed
addressing. Setting MVCD = 1 disables the indexed addressing mode such that MOVC A, @A+DPTR functions as
MOVC A, @DPTR.
DPTR1 Redirect to B. DPRB selects the source/destination register for MOVC/MOVX instructions that reference DPTR1.
When DPRB = 0, ACC is the source/destination. When DPRB = 1, B is the source/destination. DPRB does not change
the index register for MOVC instructions.
DSPR
MRW1
7
– Digital Signal Processing Configuration Register
• In some cases, both data pointers must be used simultaneously. To prevent frequent toggling
MRW0
of DPS, the AT89LP6440 supports a prefix notation for selecting the opposite data pointer
per instruction. All DPTR instructions, with the exception of JMP @A+DPTR, when prefixed
with an 0A5H opcode will use the inverse value of DPS (DPS) to select the data pointer.
Some assemblers may support this operation by using the /DPTR operand. For example, the
following code performs a block copy within EDATA:
COPY: MOVX A, @DPTR
For assemblers that do not support this notation, the 0A5H prefix must be declared in-line:
EX:
6
Figure
MOV
MOV
MOV
MOV
INC
MOVX @/DPTR, A
INC
DJNZ R7, COPY
DB
INC
SMLB
5-5. For example, MRW = 10B for normal 16-bit fixed-point operations where the lowest
5
DPCF, #00H
DPTR, #SRC
/DPTR, #DST
R7, #BLKSIZE
DPTR
/DPTR
0A5H
DPTR
SMLA
4
; DPS = 0
; load source address to dptr0
; load destination address to dptr1
; number of bytes to copy
; read source (dptr0)
; next src (dptr0+1)
; write destination (dptr1)
; next dst (dptr1+1)
; equivalent to INC /DPTR
CBE1
3
AT89LP6440 - Preliminary
CBE0
2
Reset Value = 0000 0000B
MVCD
1
DPRB
0
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