AT89LP6440-20AU Atmel, AT89LP6440-20AU Datasheet - Page 46
AT89LP6440-20AU
Manufacturer Part Number
AT89LP6440-20AU
Description
MCU 8051 64K FLASH ISP 44TQFP
Manufacturer
Atmel
Series
89LPr
Specifications of AT89LP6440-20AU
Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
8K x 8
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Package
44TQFP
Device Core
8051
Family Name
89LP
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3 V
Data Bus Width
8 Bit
Number Of Programmable I/os
38
Interface Type
2-Wire/SPI
On-chip Dac
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89LP6440-20AU
Manufacturer:
Cirrus
Quantity:
89
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10.1.3
10.1.4
46
AT89LP6440 - Preliminary
Open-drain Output
Push-pull Output
Figure 10-3. Input Circuit for P3.2, P3.3, P4.0, P4.1 and P4.2
The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor
of the port pin when the port latch contains a logic “0”. To be used as a logic output, a port con-
figured in this manner must have an external pull-up, typically a resistor tied to V
down for this mode is the same as for the quasi-bidirectional mode. The open-drain port configu-
ration is shown in
disabled during Power-down (see
ing during Power-down when configured in this mode.
Figure 10-4. Open-Drain Output
The push-pull output configuration has the same pull-down structure as both the open-drain and
the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port
latch contains a logic “1”. The push-pull mode may be used when more source current is needed
from a port output. The push-pull port configuration is shown in
Figure 10-5. Push-pull Output
Register
From Port
From Port
Register
Figure
10-4. The input circuitry of P3.2, P3.3, P4.0, P4.1 and P4.2 is not
Input
Data
Figure
Input
Data
10-3) and therefore these pins should not be left float-
PWD
Input
Data
V
CC
PWD
Figure
Port
Pin
Port
Pin
10-5.
Port
Pin
3706A–MICRO–9/09
DD
. The pull-
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