AT89LP6440-20AU Atmel, AT89LP6440-20AU Datasheet - Page 40

• Manufacturer Part Number: AT89LP6440-20AU
• Description: MCU 8051 64K FLASH ISP 44TQFP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP6440-20AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: 8051
• Family Name: 89LP
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 38
• Interface Type: 2-Wire/SPI
• On-chip Dac: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.1
40
Interrupt Response Time
AT89LP6440 - Preliminary
Table 9-1.
The interrupt flags may be set by their hardware in any clock cycle. The interrupt controller polls
the flags in the last clock cycle of the instruction in progress. If one of the flags was set in the
preceding cycle, the polling cycle will find it and the interrupt system will generate an LCALL to
the appropriate service routine as the next instruction, provided that the interrupt is not blocked
by any of the following conditions: an interrupt of equal or higher priority level is already in prog-
ress; the instruction in progress is RETI or any write to the IE, IP, IPH, IE2, IP2 or IP2H registers;
the CPU is currently forced into idle by an IAP or FDATA write. Each of these conditions will
block the generation of the LCALL to the interrupt service routine. The second condition ensures
that if the instruction in progress is RETI or any access to IE, IP, IPH, IE2, IP2 or IP2H, then at
least one more instruction will be executed before any interrupt is vectored to. The polling cycle
is repeated at the last cycle of each instruction, and the values polled are the values that were
present at the previous clock cycle. If an active interrupt flag is not being serviced because of
one of the above conditions and is no longer active when the blocking condition is removed, the
denied interrupt will not be serviced. In other words, the fact that the interrupt flag was once
active but not serviced is not remembered. Every polling cycle is new.
If a request is active and conditions are met for it to be acknowledged, a hardware subroutine
call to the requested service routine will be the next instruction executed. The call itself takes
four cycles. Thus, a minimum of five complete clock cycles elapsed between activation of an
interrupt request and the beginning of execution of the first instruction of the service routine. A
longer response time results if the request is blocked by one of the previously listed conditions. If
an interrupt of equal or higher priority level is already in progress, the additional wait time
depends on the nature of the other interrupt's service routine. If the instruction in progress is not
in its final clock cycle, the additional wait time cannot be more than 8 cycles, since the longest
instruction is 9 cycles long. If the instruction in progress is RETI with XSTK, the additional wait
time cannot be more than 14 cycles (a maximum of 5 more cycles to complete the instruction in
progress, plus a maximum of 9 cycles to complete the next instruction). Thus, in a single-inter-
Interrupt
System Reset
External Interrupt 0
Timer 0 Overflow
External Interrupt 1
Timer 1 Overflow
Serial Port Interrupt
Timer 2 Interrupt
Analog Comparator Interrupt
General-purpose Interrupt
Compare/Capture Array Interrupt
Serial Peripheral Interface Interrupt
ADC Interrupt
Two-Wire Interface Interrupt
Interrupt Vector Addresses
Source
RST or POR or BOD
IE0
TF0
IE1
TF1
RI or TI
TF2 or EXF2
CFA or CFB
GPIF
T2CCF
SPIF or MODF or TXE
ADIF
TWIF
7-0
3-0
Vector Address
3706A–MICRO–9/09
0000H
0003H
000BH
0013H
001BH
0023H
002BH
0033H
003BH
0043H
004BH
0053H
005BH