AT89LP6440-20AU Atmel, AT89LP6440-20AU Datasheet - Page 147
![MCU 8051 64K FLASH ISP 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
AT89LP6440-20AU
Manufacturer Part Number
AT89LP6440-20AU
Description
MCU 8051 64K FLASH ISP 44TQFP
Manufacturer
Atmel
Series
89LPr
Specifications of AT89LP6440-20AU
Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
8K x 8
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Package
44TQFP
Device Core
8051
Family Name
89LP
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3 V
Data Bus Width
8 Bit
Number Of Programmable I/os
38
Interface Type
2-Wire/SPI
On-chip Dac
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89LP6440-20AU
Manufacturer:
Cirrus
Quantity:
89
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22.1
22.1.1
22.1.2
3706A–MICRO–9/09
Description: The forty bits in the M register are shifted one bit to the right. Bit 39 retains its value to preserve the sign of the
Description: BREAK transfers control from normal execution to the On-Chip Debug (OCD) handler if OCD is enabled. The PC
Instruction Set Extensions
Operation: ASR
Operation: BREAK
Encoding:
Encoding:
Function: Shift MAC Accumulator Right Arithmetically
Function: Software Breakpoint (Halt execution)
ASR M
BREAK
Example: The M register holds the value 0C5B1A29384H . The following instruction,
Example: If On-Chip Debugging is allowed, the following instruction,
Cycles: 2
Cycles: 2
Bytes: 2
Bytes: 2
value. No flags are affected.
ASR M
leaves the M register holding the value 0E2D8D149C2H.
(M
(M
is left pointing to the following instruction. If OCD is disabled, BREAK acts as a double NOP. No flags are
affected.
BREAK
will halt instruction execution prior to the immediately following instruction. If debugging is not allowed, the
BREAK is treated as a double NOP.
(PC) ← (PC) + 2
n
39
) ← (M
A5
A5
) ← (M
The following instructions are extensions to the standard 8051 instruction set that provide
enhanced capabilities not found in standard 8051 devices. All extended instructions start with an
A5H escape code. For this reason random A5H reserved codes should not be placed in the
instruction stream even though other devices may have treated these as NOPs.
Other AT89LP devices may not support all of these instructions.
n + 1
39
)
) n = 0 - 38
0
0
0
0
0
0
0
0
0
0
0
0
AT89LP6440 - Preliminary
1
0
1
0
147
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