AT89LP6440-20AU Atmel, AT89LP6440-20AU Datasheet - Page 59
![MCU 8051 64K FLASH ISP 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
AT89LP6440-20AU
Manufacturer Part Number
AT89LP6440-20AU
Description
MCU 8051 64K FLASH ISP 44TQFP
Manufacturer
Atmel
Series
89LPr
Specifications of AT89LP6440-20AU
Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
8K x 8
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Package
44TQFP
Device Core
8051
Family Name
89LP
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3 V
Data Bus Width
8 Bit
Number Of Programmable I/os
38
Interface Type
2-Wire/SPI
On-chip Dac
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89LP6440-20AU
Manufacturer:
Cirrus
Quantity:
89
12. Enhanced Timer 2
3706A–MICRO–9/09
The AT89LP6440 includes a 16-bit Timer/Counter 2 with the following features:
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The
type of operation is selected by bit C/T2 in the SFR T2CON. Timer 2 has three operating modes:
capture, auto-reload (up or down counting), and baud rate generator. The modes are selected
by bits in T2CON and T2MOD, as shown in
the Compare/Capture Array (See
Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the register is incre-
mented every clock cycle. Since a clock cycle consists of one oscillator period, the count rate is
equal to the oscillator frequency. The timer rate can be prescaled by a value between 1 and 16
using the Timer Prescaler (see
In the Counter function, the register is incremented in response to a 1-to-0 transition at its corre-
sponding external input pin, T2. In this function, the external input is sampled every clock cycle.
When the samples show a high in one cycle and a low in the next cycle, the count is incre-
mented. The new count value appears in the register during the cycle following the one in which
the transition was detected. Since two clock cycles are required to recognize a 1-to-0 transition,
the maximum count rate is 1/2 of the oscillator frequency. To ensure that a given level is sam-
pled at least once before it changes, the level should be held for at least one full clock cycle.
Table 12-1.
The following definitions for Timer 2 are used in the subsequent paragraphs:
Table 12-2.
RCLK + TCLK
• 16-bit timer/counter with one 16-bit reload/capture register
• One external reload/capture input
• Up/Down counting mode with external direction control
• UART baud rate generation
• Output-pin toggle on timer overflow
• Dual slope symmetric operating modes
BOTTOM
Symbol
MAX
TOP
MIN
X
X
0
0
0
1
Timer 2 Operating Modes
Timer 2 Definitions
Definition
0000H
FFFFH
16-bit value of {RCAP2H,RCAP2L} (standard modes)
16-bit value of {RCAP2H,RCAP2L} (enhanced modes)
CP/RL2
X
X
X
0
0
1
DCEN
X
X
X
X
0
1
Table 6-2 on page
Section 13. “Compare/Capture Array” on page
T2OE
X
X
0
0
0
1
Table
AT89LP6440 - Preliminary
12-3. Timer 2 also serves as the time base for
TR2
32).
1
1
1
1
1
0
MODE
16-bit Auto-reload
16-bit Auto-reload Up-Down
16-bit Capture
Baud Rate Generator
Frequency Generator
(Off)
68).
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