AT89LP6440-20AU Atmel, AT89LP6440-20AU Datasheet - Page 163

• Manufacturer Part Number: AT89LP6440-20AU
• Description: MCU 8051 64K FLASH ISP 44TQFP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP6440-20AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: 8051
• Family Name: 89LP
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 38
• Interface Type: 2-Wire/SPI
• On-chip Dac: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.4
Table 25-3.
25.5
25.6
Table 25-4.
3706A–MICRO–9/09
Symbol
LOAD
SUCCESS
WRTINH
BUSY
Bit
Mode
Status Register
DATA Polling
Flash Security
1
2
3
Program Lock Bits (by address)
Function
Load flag. Cleared low by the load page buffer command and set high by the next memory write. This flag signals that
the page buffer was previously loaded with data by the load page buffer command.
Success flag. Cleared low at the start of a programming cycle and will only be set high if the programming cycle
completes without interruption from the brownout detector.
Write Inhibit flag. Cleared low by the brownout detector (BOD) whenever programming is inhibited due to V
below the minimum required programming voltage. If a BOD episode occurs during programming, the SUCCESS flag
will remain low after the cycle is complete.
Busy flag. Cleared low whenever the memory is busy programming or if write is currently inhibited.
Status
Lock Bit Protection Modes
–
7
Register
FFh
00h
00h
00h
The current state of the memory may be accessed by reading the status register. The status reg-
ister is shown in
The AT89LP6440 implements DATA polling to indicate the end of a programming cycle. While
the device is busy, any attempted read of the last byte written will return the data byte with the
MSB complemented. Once the programming cycle has completed, the true value will be acces-
sible. During Erase the data is assumed to be FFH and DATA polling will return 7FH. When
writing multiple bytes in a page, the DATA value will be the last data byte loaded before pro-
gramming begins, not the written byte with the highest physical address within the page.
The AT89LP6440 provides two Lock Bits for Flash Code and Data Memory security. Lock bits
can be left unprogrammed (FFh) or programmed (00h) to obtain the protection levels listed in
Table
programming of all memory spaces, including the User Signature Array and User Configuration
Fuses. User fuses must be programmed before enabling Lock bit mode 2 or 3. Lock bit mode 3
implements mode 2 and also blocks reads from the code and data memories; however, reads of
the User Signature Array, Atmel Signature Array, and User Configuration Fuses are still allowed.
The Lock Bits will not disable FDATA or IAP programming initiated by the application software.
–
6
25-4. Lock bits can only be erased (set to FFh) by Chip Erase. Lock bit mode 2 disables
FFh
FFh
01h
00h
Table
–
5
25-3.
Protection Mode
No program lock features
Further programming of the Flash is disabled
Further programming of the Flash is disabled and verify (read) is also
disabled; OCD is disabled
–
4
LOAD
3
AT89LP6440 - Preliminary
SUCCESS
2
WRTINH
1
BUSY
0
DD
falling
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