AT89LP6440-20AU Atmel, AT89LP6440-20AU Datasheet - Page 77

• Manufacturer Part Number: AT89LP6440-20AU
• Description: MCU 8051 64K FLASH ISP 44TQFP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP6440-20AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: 8051
• Family Name: 89LP
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 38
• Interface Type: 2-Wire/SPI
• On-chip Dac: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.4.1
13.4.2
3706A–MICRO–9/09
Asymmetrical PWM
Symmetrical PWM
For Asymmetrical PWM, Timer 2 should be configured for Auto-Reload mode and Count Mode 1
(CP/RL2 = 0, DCEN = 0, T2CM1-0 = 01B). Asymmetrical PWM uses single slope operation as
shown in
TOM. In non-inverting mode, the output CCx is set on the compare match between Timer 2
(TL2, TH2) and the channel data register (CCxL, CCxH), and cleared at BOTTOM. In inverting
mode, the output CCx is cleared on the compare match between Timer 2 and the data register,
and set at BOTTOM. The resulting asymmetrical output waveform is left-edge aligned.
The TOP value in RCAP2L and RCAP2H is double buffered such that the output frequency is
only updated at the TOP to BOTTOM overflow. The channel data register (CCxL, CCxH) is also
double-buffered such that the duty cycle is only updated at the TOP to BOTTOM overflow to pre-
vent glitches. The output frequency and duty cycle for asymmetrical PWM are given by the
following equations:
The extreme compare values represent special cases when generating a PWM waveform. If the
compare value is set equal to (or greater than) TOP, the output will remain low or high for non-
inverting and inverting modes, respectively. If the compare value is set to BOTTOM (0000H), the
output will remain high or low for non-inverting and inverting modes, respectively.
Figure 13-8. Asymmetrical (Edge-Aligned) PWM
For Symmetrical PWM, Timer 2 should be configured for Auto-Reload mode and Count Mode 2
or 3 (CP/RL2 = 0, DCEN = 0, T2CM1-0 = 1xB). Symmetrical PWM uses dual-slope operation as
shown in
MIN. The timer is equal to TOP for exactly one clock cycle. In non-inverting mode, the output
CCx is cleared on the up-count compare match between Timer 2 (TL2, TH2) and the channel
data register (CCxL, CCxH), and set at the down-count compare match. In inverting mode, the
output CCx is set on the up-count compare match between Timer 2 and the data register, and
cleared at the down-count compare match. The resulting symmetrical PWM output waveform is
{RCAP2H,RCA2L}
{CCxH,CCxL}
Figure
Figure
Non-Inverting:
Non-inverted
Inverted
13-9. The timer counts up from MIN to TOP and then counts down from TOP to
13-8. The timer counts up from BOTTOM to TOP and then restarts from BOT-
CCx
Inverting:
Duty Cycle
f
OUT
Duty Cycle
=
--------------------------------------------------------------- -
{
RCAP2H RCAP2L
Oscillator Frequency
=
100%
CP/RL2 = 0, T2CM
=
,
AT89LP6440 - Preliminary
100%
×
{
------------------------------------------------------------------------------------------------------------ -
RCAP2H RCAP2L
×
}
--------------------------------------------------------------- -
{
+
RCAP2H RCAP2L
{
1
1-0
RCAP2H RCAP2L
,
×
{
CCxH CCxL
= 01B, DCEN = 0
-------------------- -
TPS
,
1
+
,
,
}
1
–
{
}
CCxH CCxL
}
+
}
1
+
,
1
}
+
1
77