AT89LP6440-20AU Atmel, AT89LP6440-20AU Datasheet - Page 126

• Manufacturer Part Number: AT89LP6440-20AU
• Description: MCU 8051 64K FLASH ISP 44TQFP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP6440-20AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: 8051
• Family Name: 89LP
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 38
• Interface Type: 2-Wire/SPI
• On-chip Dac: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19. Dual Analog Comparators
Figure 19-1. Dual Comparator Block Diagram
126
(P2.7) AIN3
(P2.6) AIN2
(P2.5) AIN1
(P2.4) AIN0
AT89LP6440 - Preliminary
Figure 18-15. Combining Several TWI Modes to Access a Serial EEPROM
The AT89LP6440 provides two analog comparators. The analog comparators have the following
features:
A block diagram of the dual analog comparators with relevant connections is shown in
19-1. Input options allow the comparators to function in a number of different configurations as
shown in
tive input is greater than the negative input. Otherwise the output is a zero. Setting the CENA
(ACSRA.3) and CENB (ACSRB.3) bits enable Comparator A and B respectively. The user must
• Internal 3-level Voltage Reference (1.125V, 1.25V, 1.375V)
• Four Shared Analog Input Channels
• Selectable Interrupt Conditions
• Hardware Debouncing Modes
S
– Configure as Multiple Input Window Comparator
– High- or Low-level
– Rising- or Falling-edge
– Output Toggle
S = START
Figure
CSB1
CSA1
Transmitted from master to slave
CSB0
CSA0
SLA+W
11
10
01
00
00
01
10
11
19-4. Comparator operation is such that the output is a logic “1” when the posi-
A
Master Transmitter
11
10
01
00
00
01
10
11
ADDRESS
RFB1
RFA1
RFB0
RFA0
B
A
V
V
V
AREF+Δ
AREF
AREF-Δ
A
Rs = REPEATED START
CMB2
CMB1
CMB0
CMA2
CMA1
CMA0
Rs
Transmitted from slave to master
SLA+R
CFB
CFA
A
CMPB (P4.7)
CMPA (P4.6)
Master Receiver
EC
DATA
3706A–MICRO–9/09
P = STOP
Interrupt
A
P
Figure