AT89LP6440-20AU Atmel, AT89LP6440-20AU Datasheet - Page 136

• Manufacturer Part Number: AT89LP6440-20AU
• Description: MCU 8051 64K FLASH ISP 44TQFP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP6440-20AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: 8051
• Family Name: 89LP
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 38
• Interface Type: 2-Wire/SPI
• On-chip Dac: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.2
136
DAC Operation
AT89LP6440 - Preliminary
Figure 20-3. Equivalent Analog Input Model
The DAC converts a 10-bit signed digital value to an analog output voltage through successive
approximation. The DAC always operates in differential mode, outputting a voltage differential
between its positive (P2.2) and negative (P2.3) outputs with a common mode of AV
minimum value represents zero difference and the maximum values represent a difference of
positive or negative V
The DAC is enabled by setting the ADCE and DAC bits in DADC. Some settling time is required
for the reference circuits to stabilize after the DAC is enabled. The DAC does not have multiple
output channels and the DIFF, ACON and ACS bits have no effect in DAC mode. P2.2 and P2.3
are automatically forced to input-only mode while the DAC is enabled.
A timing diagram of a DAC conversion is shown in
clock cycles to complete. Construction of the analog output starts in the second cycle of the con-
version and the DAC will allow the new value to propagate to the outputs during cycle 7, after the
5 MSBs are complete. At the end of the conversion, the interrupt flag is set. An additional 1 ADC
clock cycle and up to 2 system clock cycles may be required to synchronize ADIF with the rest of
the system. The DADL and DADH registers hold the value to be output and are write-only during
DAC mode. An internal buffer samples DADH/DADL at the start of the conversion and holds the
value constant for the remainder of the conversion. One system clock cycle is required to trans-
fer the contents of DADH/DADL into the buffer at the start of the conversion and therefore the
ADC clock frequency must always be equal to or less than the system clock frequency during
DAC mode to ensure that the buffer is updated before the second cycle.
Figure 20-4. DAC Timing Diagram
The equivalent model for the analog output circuitry is illustrated in
put resistance of the DAC must drive the pin capacitance and any external load on the pin.
Cycle Number
ADC Clock
GO/BSY
ADIF
DADH
DADL
ADCn
1
C
10 pF
REF
PIN
2
Initialize Circuitry
minus 1 LSB.
=
3
MSB of Output
LSB of Output
Begin Output
4
One Conversion
5
6
10 kΩ
R
IN
7
=
8
Figure
Conversion
Complete
9
20-4. The conversion requires 11 ADC
10
R
10 kΩ
MUX
11
=
Figure
Next Conversion
1
20-5. The series out-
C
2 pF
S/H
2
Initialize
=
3706A–MICRO–9/09
3
DD
/2. The