AT89LP6440-20AU Atmel, AT89LP6440-20AU Datasheet - Page 68

• Manufacturer Part Number: AT89LP6440-20AU
• Description: MCU 8051 64K FLASH ISP 44TQFP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP6440-20AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: 8051
• Family Name: 89LP
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 38
• Interface Type: 2-Wire/SPI
• On-chip Dac: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 12-9. Timer 2 in Clock-out Mode
13. Compare/Capture Array
68
AT89LP6440 - Preliminary
T2EX PIN
T2 PIN
The AT89LP6440 includes a four channel Compare/Capture Array (CCA) that performs a variety
of timing operations including input event capture, output compare waveform generation and
pulse width modulation (PWM). Timer 2 serves as the time base for the four 16-bit compare/cap-
ture modules. The CCA has the following features:
The block diagram of the CCA is given in
register and a 16-bit data register. The channel registers are not directly accessible. The CCA
address register T2CCA provides an index into the array. The control, data low and data high
bytes of the currently indexed channel are accessed through the T2CCC, T2CCL and T2CCH
registers respectively.
Each channel can be individually configured for capture or compare mode. Capture mode is the
default setting. During capture mode the current value of the time base is copied into the chan-
nel’s data register when the specified external or internal event occurs. An interrupt flag is set at
the same time and the time base may be optionally cleared. To enable compare mode, the
CCMx bit in the channel’s control register (CCCx) should be set to 1. In compare mode an inter-
rupt flag is set and an output pin is optionally toggled when the value of the time base matches
the value of the channel’s data register. The time base may also be optionally cleared on a com-
pare match.
Timer 2 must be running (TR2 = 1) in order to perform captures or compares with the CCA.
However, when TR2 = 0 the external capture events will still set their associated flags and may
be used as additional external interrupts.
OSC
• Four 16-bit Compare/Capture channels
• Common time base provided by Timer 2
• Selectable external and internal capture events including pin change, timer overflow and
• Symmetric/Asymmetric PWM with selectable polarity
• Multi-phasic PWM outputs
• One interrupt flag per channel with a common interrupt vector
comparator output change
÷TPS
TRANSITION
DETECTOR
C/T2
EXEN2
TR2
Figure
RCAP2L
TL2
÷2
13-1. Each channel consists of an 8-bit control
EXF2
RCAP2H
TH2
T2OE
INTERRUPT
TIMER 2
3706A–MICRO–9/09