AT89LP6440-20AU Atmel, AT89LP6440-20AU Datasheet - Page 22

• Manufacturer Part Number: AT89LP6440-20AU
• Description: MCU 8051 64K FLASH ISP 44TQFP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP6440-20AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: 8051
• Family Name: 89LP
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 38
• Interface Type: 2-Wire/SPI
• On-chip Dac: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5. Enhanced CPU
22
AT89LP6440 - Preliminary
The AT89LP6440 uses an enhanced 8051 CPU that runs at 6 to 12 times the speed of standard
8051 devices (or 3 to 6 times the speed of X2 8051 devices). The increase in performance is
due to two factors. First, the CPU fetches one instruction byte from the code memory every clock
cycle. Second, the CPU uses a simple two-stage pipeline to fetch and execute instructions in
parallel. This basic pipelining concept allows the CPU to obtain up to 1 MIPS per MHz. A simple
example is shown in
The 8051 instruction set allows for instructions of variable length from 1 to 3 bytes. In a single-
clock-per-byte-fetch system this means each instruction takes at least as many clocks as it has
bytes to execute. The majority of instructions in the AT89LP6440 follow this rule: the instruction
execution time in clock cycles equals the number of bytes per instruction, with a few exceptions.
Branches and Calls require an additional cycle to compute the target address and some other
complex instructions require multiple cycles.
more detailed information on individual instructions.
and 2-byte instructions.
Figure 5-1.
Figure 5-2.
Register Operand Fetch
ALU Operation Execute
Fetch Next Instruction
Total Execution Time
(n+1)
(n+2)
Result Write Back
Parallel Instruction Fetches and Executions
Single-cycle ALU Operation (Example: INC R0)
System Clock
n
System Clock
th
th
th
Instruction
Instruction
Instruction
Figure
5-1.
Fetch
T
T
n
1
See “Instruction Set Summary” on page 143.
Figures 5-2 and 5-3
Execute
Fetch
T
n+1
T
2
Execute
show examples of 1-
Fetch
T
n+2
T
3
3706A–MICRO–9/09
for