AT89LP6440-20AU Atmel, AT89LP6440-20AU Datasheet - Page 120

• Manufacturer Part Number: AT89LP6440-20AU
• Description: MCU 8051 64K FLASH ISP 44TQFP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP6440-20AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: 8051
• Family Name: 89LP
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 38
• Interface Type: 2-Wire/SPI
• On-chip Dac: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 18-8.
120
Status
Code
(TWSR)
60h
68h
70h
78h
80h
AT89LP6440 - Preliminary
Status of the Two-wire
Serial Bus and Two-wire
Serial Interface Hardware
Own SLA+W has been
received; ACK has been
returned
Arbitration lost in SLA+R/W
as master; own SLA+W has
been received; ACK has
been returned
General call address has
been received; ACK has
been returned
Arbitration lost in SLA+R/W
as master; General call
address has been received;
ACK has been returned
Previously addressed with
own SLA+W; data has been
received; ACK has been
returned
Status Codes for Slave Receiver Mode
TWEN must be written to one to enable the TWI. The AA bit must be written to one to enable the
acknowledgment of the device’s own slave address or the general call address. STA and STO
must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own
slave address (or the general call address if enabled) followed by the data direction bit. If the
direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST mode is entered. After
its own slave address and the write bit have been received, the TWIF flag is set and a valid sta-
tus code can be read from TWSR. The status code is used to determine the appropriate
software action. The appropriate action to be taken for each status code is detailed in
8. The Slave Receiver mode may also be entered if arbitration is lost while the TWI is in the Mas-
ter mode (see states 68h and 78h).
If the AA bit is reset during a transfer, the TWI will return a “Not Acknowledge” (“1”) to SDA after
the next received data byte. This can be used to indicate that the slave is not able to receive any
more bytes. While AA is zero, the TWI does not acknowledge its own slave address. However,
the Two-wire Serial Bus is still monitored and address recognition may resume at any time by
setting AA. This implies that the AA bit may be used to temporarily isolate the TWI from the Two-
wire Serial Bus.
.
To/from TWDR
No action
No action
No action
No action
No action
No action
No action
No action
Read data byte
Read data byte
Application Software Response
STA
X
X
X
X
X
X
X
X
X
X
STO
0
0
0
0
0
0
0
0
0
0
To TWCR
TWIF
1
1
1
1
1
1
1
1
1
1
AA
0
1
0
1
0
1
0
1
0
1
Next Action Taken by TWI Hardware
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be
returned
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be
returned
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be
returned
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be
returned
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be
returned
3706A–MICRO–9/09
Table 18-