AT89LP6440-20AU Atmel, AT89LP6440-20AU Datasheet - Page 130

MCU 8051 64K FLASH ISP 44TQFP

AT89LP6440-20AU

Manufacturer Part Number
AT89LP6440-20AU
Description
MCU 8051 64K FLASH ISP 44TQFP
Manufacturer
Atmel
Series
89LPr
Datasheets

Specifications of AT89LP6440-20AU

Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
8K x 8
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Package
44TQFP
Device Core
8051
Family Name
89LP
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3 V
Data Bus Width
8 Bit
Number Of Programmable I/os
38
Interface Type
2-Wire/SPI
On-chip Dac
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89LP6440-20AU
Manufacturer:
Cirrus
Quantity:
89
Part Number:
AT89LP6440-20AU
Manufacturer:
Atmel
Quantity:
10 000
Table 19-1.
Notes:
130
Symbol
CSA [1-0]
CONA
CFA
CENA
CMA [2-0]
ACSRA = 97H
Not Bit Addressable
Bit
1. CONA must be cleared to 0 before changing CSA[1-0].
2. Debouncing modes require the use of Timer 1 to generate the sampling delay.
AT89LP6440 - Preliminary
Function
Comparator A Positive Input Channel Select
CSA1
0
0
1
1
Comparator A Input Connect. When CONA = 1 the analog input pins are connected to the comparator. When CONA = 0
the analog input pins are disconnected from the comparator. CONA must be cleared to 0 before changing CSA[1-0] or
RFA[1-0].
Comparator A Interrupt Flag. Set when the comparator output meets the conditions specified by the CMA [2-0] bits and
CENA is set. The flag must be cleared by software. The interrupt may be enabled/disabled by setting/clearing bit 6 of IE.
Comparator A Enable. Set this bit to enable the comparator. Clearing this bit will force the comparator output low and
prevent further events from setting CFA. When CENA = 1 the analog input pins, P2.4—P2.7, have their digital inputs
disabled if they are configured in input-only mode.
Comparator A Interrupt Mode
CMA2
0
0
0
0
1
1
1
1
ACSRA
CSA1
7
– Analog Comparator A Control & Status Register
CSA0
0
1
0
1
CMA1
0
0
1
1
0
0
1
1
CSA0
6
A+ Channel
AIN0 (P2.4)
AIN1 (P2.5)
AIN2 (P2.6)
AIN3 (P2.7)
CMA0
0
1
0
1
0
1
0
1
CONA
5
Interrupt Mode
Negative (Low) level
Positive edge
Toggle with debouncing
Positive edge with debouncing
Negative edge
Toggle
Negative edge with debouncing
Positive (High) level
(1)
CFA
4
(2)
CENA
3
(2)
(2)
CMA2
2
Reset Value = 0000 0000B
CMA1
1
CMA0
3706A–MICRO–9/09
0

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