AT89LP6440-20AU Atmel, AT89LP6440-20AU Datasheet - Page 148
![MCU 8051 64K FLASH ISP 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
AT89LP6440-20AU
Manufacturer Part Number
AT89LP6440-20AU
Description
MCU 8051 64K FLASH ISP 44TQFP
Manufacturer
Atmel
Series
89LPr
Specifications of AT89LP6440-20AU
Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
8K x 8
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Package
44TQFP
Device Core
8051
Family Name
89LP
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3 V
Data Bus Width
8 Bit
Number Of Programmable I/os
38
Interface Type
2-Wire/SPI
On-chip Dac
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89LP6440-20AU
Manufacturer:
Cirrus
Quantity:
89
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22.1.3
22.1.4
148
Description: CJNE compares the magnitudes of the Accumulator and indirect RAM location and branches if their values are
Description: CLR M clears the 40-bit M register. No flags are affected.
Operation: CJNE
Operation: JMP
Encoding:
Encoding:
AT89LP6440 - Preliminary
Function: Compare and Jump if Not Equal
Function: Clear MAC Accumulator
CJNE A, @R
CLR M
Example: The Accumulator contains 34H. Register 0 contains 78H and 78H contains 56H. The first instruction in the
Example: The M registercontains 123456789AH. The following instruction,
Cycles: 9
Cycles: 2
Bytes: 2
Bytes: 2
not equal. The branch destination is computed by adding the signed relative-displacement in the last instruction
byte to the PC, after incrementing the PC to the start of the next instruction. The carry flag is set if the unsigned
integer value of ACC is less than the unsigned integer value of the indirect location; otherwise, the carry is
cleared. Neither operand is affected.
sequence,
;
NOT_EQ:
;
sets the carry flag and branches to the instruction at label NOT_EQ. By testing the carry flag, the second
instruction determines whether ACC is greater or less than the location pointed to by R0.
(PC) ← (PC) + 3
IF (A) ≠ ((R
THEN
IF (A) < ((R
THEN
ELSE
CLR M
leaves the M register set to 0000000000H.
(M) ← 0
i
, rel
A5
A5
CJNE
(PC) ← (PC) + relative offset
(C) ← 1
(C) ← 0
JC
. . . . . .
. . . . . .
i
i
))
))
A, @R0, NOT_EQ
REQ_LOW .. ;IF ACC< @R0.
...... ...... ; ACC = @R0.
...... ...... ;ACC > @R0.
1
1
0
1
1
1
1
0
0
0
1
1
1
0
0
i
rel. address
3706A–MICRO–9/09
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