AT89LP6440-20AU Atmel, AT89LP6440-20AU Datasheet - Page 169

• Manufacturer Part Number: AT89LP6440-20AU
• Description: MCU 8051 64K FLASH ISP 44TQFP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP6440-20AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: 8051
• Family Name: 89LP
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 38
• Interface Type: 2-Wire/SPI
• On-chip Dac: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.9.6
3706A–MICRO–9/09
Timing Parameters
The timing parameters for
Figure 25-13
Table 25-7.
Note:
Symbol
t
t
PWRDN
PWRUP
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SHSL
SLSH
t
t
CLCL
t
t
t
t
t
AWR
POR
RHZ
SCK
t
t
SOH
SOV
POH
POV
SOE
SOX
POE
POX
SSE
SSD
ERS
RLZ
STL
ZSS
SSZ
SIH
PIH
WR
SIS
PIS
SR
SF
1. t
SCK
are shown in
Programming Interface Timing Parameters
is independent of t
System Clock Cycle Time
Power On to SS High Time
Power-on Reset Time
SS Tristate to Power Off
RST Low to I/O Tristate
RST Low Settling Time
RST High to SS Tristate
Serial Clock Cycle Time
Clock High Time
Clock Low Time
Rise Time
Fall Time
Serial Input Setup Time
Serial Input Hold Time
Serial Output Hold Time
Serial Output Valid Time
Parallel Input Setup Time
Parallel Input Hold Time
Parallel Output Hold Time
Parallel Output Valid Time
Serial Output Enable Time
Serial Output Disable Time
Parallel Output Enable Time
Parallel Output Disable Time
SS Enable Lead Time
SS Disable Lag Time
SCK Setup to SS Low
SCK Hold after SS High
Write Cycle Time
Write Cycle with Auto-Erase Time
Chip Erase Cycle Time
Parameter
Figure
Table
CLCL
.
25-7,
.
Figure
AT89LP6440 - Preliminary
25-8,
Figure
200
t
t
t
Min
100
CLCL
SLSH
SLSH
25-9,
2.5
7.5
10
75
50
10
10
10
10
25
25
0
0
5
(1)
Figure
25-10,
2 t
2 t
Max
100
60
25
25
10
35
10
35
10
25
10
25
CLCL
CLCL
1
Figure 25-12
Units
ms
ms
ms
ns
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
and
169