AT89LP6440-20AU Atmel, AT89LP6440-20AU Datasheet - Page 125

• Manufacturer Part Number: AT89LP6440-20AU
• Description: MCU 8051 64K FLASH ISP 44TQFP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP6440-20AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: 8051
• Family Name: 89LP
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 38
• Interface Type: 2-Wire/SPI
• On-chip Dac: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.6.5
Table 18-10. Miscellaneous States
18.6.6
3706A–MICRO–9/09
Status
Code
(TWSR)
F8h
00h
Miscellaneous States
Combining Several TWI Modes
Status of the Two-wire
Serial Bus and Two-wire
Serial Interface hardware
No relevant state
information available;
TWIF = “0”
Bus error due to an illegal
START or STOP condition
There are two status codes that do not correspond to a defined TWI state, see
Status F8h indicates that no relevant information is available because the TWIF flag is not set.
This occurs between other states, and when the TWI is not involved in a serial transfer.
Status 00h indicates that a bus error has occurred during a Two-wire Serial Bus transfer. A bus
error occurs when a START or STOP condition occurs at an illegal position in the format frame.
Examples of such illegal positions are during the serial transfer of an address byte, a data byte,
or an acknowledge bit. When a bus error occurs, TWIF is set. To recover from a bus error, the
STO flag must set and TWIF must be cleared. This causes the TWI to enter the not addressed
Slave mode and to clear the STO flag (no other bits in TWCR are affected). The SDA and SCL
lines are released, and no STOP condition is transmitted.
In some cases, several TWI modes must be combined in order to complete the desired action.
Consider for example reading data from a serial EEPROM. Typically, such a transfer involves
the following steps:
Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct
the Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data
must be read from the Slave, implying the use of the MR mode. Thus, the transfer direction must
be changed. The Master must keep control of the bus during all these steps, and the steps
should be carried out as an atomic operation. If this principle is violated in a multi-master sys-
tem, another Master can alter the data pointer in the EEPROM between steps 2 and 3, and the
Master will read the wrong data location. Such a change in transfer direction is accomplished by
transmitting a REPEATED START between the transmission of the address byte and reception
of the data. After a REPEATED START, the Master keeps ownership of the bus. The following
figure shows the flow in this transfer.
1. The transfer must be initiated.
2. The EEPROM must be instructed what location should be read.
3. The reading must be performed.
4. The transfer must be finished.
To/from TWDR
No action
No action
Application Software Response
STA
0
STO
1
To TWCR
No action
TWIF
1
AT89LP6440 - Preliminary
AA
X
Next Action Taken by TWI Hardware
Wait or proceed current transfer
Only the internal hardware is affected, no STOP
condition is sent on the bus. In all cases, the
bus is released and STO is cleared.
Table
18-10.
125