ATMEGA16HVA-4CKU Atmel, ATMEGA16HVA-4CKU Datasheet - Page 110
![MCU AVR 16K FLASH 4MHZ 36-LGA](/photos/12/32/123221/36ck1-lga_sml.jpg)
ATMEGA16HVA-4CKU
Manufacturer Part Number
ATMEGA16HVA-4CKU
Description
MCU AVR 16K FLASH 4MHZ 36-LGA
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16HVA-4CKU.pdf
(196 pages)
Specifications of ATMEGA16HVA-4CKU
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
7
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 9 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 85°C
Package / Case
36-LGA
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200, ATAVRSB201
Minimum Operating Temperature
- 20 C
On-chip Adc
12 bit, 5 Channel
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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19.7.3
19.7.4
110
ATmega8HVA/16HVA
CADICH and CADICL - CC-ADC Instantaneous Current
CADAC3, CADADC2, CADAC1, CADAC0 - CC-ADC Accumulate Current
When a CC-ADC Instantaneous Current conversion is complete, the result is found in these two
registers. CADIC[15:0] represents the converted result in 2's complement format. CADIC[12:0]
are the 13-bit ADC result (including sign), while CADIC[15:13] are the sign extension bits.
When CADICL is read, the CC-ADC Instantaneous Current register is not updated until CADCH
is read. Reading the registers in the sequence CADICL, CADICH will ensure that consistent val-
ues are read. When a conversion is completed, both registers must be read before the next
conversion is completed, otherwise data will be lost.
The CADAC3, CADAC2, CADAC1 and CADAC0 Registers contain the Accumulate Current
measurements in 2's complement format. CADAC[17:0] are the 18-bit ADC result (including
sign), while CADAC[31:18] are the sign extension bits.
When CADAC0 is read, the CC-ADC Accumulate Current register is not updated until CADAC3
is read. Reading the registers in the sequence CADAC0, CADAC1, CADAC2, CADAC3 will
ensure that consistent values are read. When a conversion is completed, all four registers must
be read before the next conversion is completed, otherwise data will be lost.
Bit
(0xE9)
(0xE8)
Read/Write
Initial Value
Bit
(0xE3)
(0xE2)
(0xE1)
(0xE0)
Read/Write
Initial Value
15
R
R
31
23
15
7
0
0
R
R
R
7
0
0
0
14
30
22
14
R
R
6
0
0
R
R
R
6
0
0
0
13
29
21
13
R
R
5
0
0
R
R
R
5
0
0
0
12
28
20
12
CADAC[31:24]
CADAC[23:16]
R
R
4
0
0
R
R
R
4
CADAC[15:8]
0
0
0
CADIC[15:8]
CADAC[7:0]
CADIC[7:0]
11
27
19
11
R
R
3
0
0
R
R
R
3
0
0
0
10
26
18
10
R
R
2
0
0
R
R
R
2
0
0
0
25
17
R
R
R
R
R
9
1
0
0
9
1
0
0
0
24
16
R
R
R
R
R
8
0
0
0
8
0
0
0
0
8024A–AVR–04/08
CADAC3
CADAC2
CADAC1
CADAC0
CADICH
CADICL
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