ATMEGA16HVA-4CKU Atmel, ATMEGA16HVA-4CKU Datasheet - Page 86

• Manufacturer Part Number: ATMEGA16HVA-4CKU
• Description: MCU AVR 16K FLASH 4MHZ 36-LGA
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16HVA-4CKU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 7
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 9 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-LGA
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200, ATAVRSB201
• Minimum Operating Temperature: - 20 C
• On-chip Adc: 12 bit, 5 Channel
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.9
86
Accessing Registers in 16-bit Mode
ATmega8HVA/16HVA
Figure 17-8. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f
shows the setting of OCFnA and the clearing of TCNTn in CTC mode.
Figure 17-9. Timer/Counter Timing Diagram, CTC mode, with Prescaler (f
In 16-bit mode (the TCWn bit is set to one) the TCNTnH/L and OCRnB/A are 16-bit registers that
can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte
accessed using two read or write operations. The 16-bit Timer/Counter has a single 8-bit register
for temporary storing of the high byte of the 16-bit access. The same temporary register is
shared between all 16-bit registers. Accessing the low byte triggers the 16-bit read or write oper-
ation. When the low byte of a 16-bit register is written by the CPU, the high byte stored in the
temporary register, and the low byte written, are both copied into the 16-bit register in the same
clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit
register is copied into the temporary register in the same clock cycle as the low byte is read.
There is one exception in the temporary register usage. In the Output Compare mode the 16-bit
Output Compare Register OCRnB/A is read without the temporary register, because the Output
Compare Register contains a fixed value that is only changed by CPU access. However, in 16-
bit Input Capture mode the ICRn register formed by the OCRnA and OCRnB registers must be
accessed with the temporary register.
To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low
byte must be read before the high byte.
TCNTn
TCNTn
(clk
(clk
OCRnx
OCFnx
(CTC)
OCRnx
OCFnx
clk
clk
clk
clk
I/O
PCK
I/O
Tn
PCK
Tn
/8)
/8)
OCRnx - 1
TOP - 1
OCRnx
TOP
OCRnx Value
TOP
OCRnx + 1
BOTTOM
clk_I/O
BOTTOM + 1
OCRnx + 2
/8)
clk_I/O
8024A–AVR–04/08
/8)