ATMEGA16HVA-4CKU Atmel, ATMEGA16HVA-4CKU Datasheet - Page 85

• Manufacturer Part Number: ATMEGA16HVA-4CKU
• Description: MCU AVR 16K FLASH 4MHZ 36-LGA
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16HVA-4CKU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 7
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 9 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-LGA
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200, ATAVRSB201
• Minimum Operating Temperature: - 20 C
• On-chip Adc: 12 bit, 5 Channel
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.7.1
17.7.2
17.8
8024A–AVR–04/08
Timer/Counter Timing Diagrams
Compare Match Blocking by TCNT0 Write
Using the Output Compare Unit
All CPU write operations to the TCNTnH/L Register will block any Compare Match that occur in
the next timer clock cycle, even when the timer is stopped. This feature allows OCRnB/A to be
initialized to the same value as TCNTn without triggering an interrupt when the Timer/Counter
clock is enabled.
Since writing TCNTnH/L will block all Compare Matches for one timer clock cycle, there are risks
involved when changing TCNTnH/L when using the Output Compare Unit, independently of
whether the Timer/Counter is running or not. If the value written to TCNTnH/L equals the
OCRnB/A value, the Compare Match will be missed.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set.
The figure shows the count sequence close to the MAX value.
Figure 17-6. Timer/Counter Timing Diagram, no Prescaling
Figure 17-7 on page 85
Figure 17-7. Timer/Counter Timing Diagram, with Prescaler (f
Figure 17-8 on page 86
TCNTn
TCNTn
(clk
(clk
TOVn
TOVn
clk
clk
clk
clk
I/O
I/O
I/O
Tn
I/O
Tn
/1)
/8)
Figure 17-6 on page 85
shows the same timing data, but with the prescaler enabled.
shows the setting of OCFnA and OCFnB in Normal mode.
MAX - 1
MAX - 1
contains timing data for basic Timer/Counter operation.
MAX
MAX
ATmega8HVA/16HVA
BOTTOM
BOTTOM
clk_I/O
/8)
Tn
) is therefore shown as a
BOTTOM + 1
BOTTOM + 1
85