ATMEGA16HVA-4CKU Atmel, ATMEGA16HVA-4CKU Datasheet - Page 112

• Manufacturer Part Number: ATMEGA16HVA-4CKU
• Description: MCU AVR 16K FLASH 4MHZ 36-LGA
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16HVA-4CKU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 7
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 9 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-LGA
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200, ATAVRSB201
• Minimum Operating Temperature: - 20 C
• On-chip Adc: 12 bit, 5 Channel
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20. Voltage ADC – 5-channel General Purpose 12-bit Sigma-Delta ADC
20.1
20.2
20.3
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Features
Overview
Operation
ATmega8HVA/16HVA
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The ATmega8HVA/16HVA features a 12-bit Sigma-Delta ADC.
The Voltage ADC (V-ADC) is connected to five different sources through the Input Multiplexer.
There are two differential channels for Cell Voltage measurements. These channels are scaled
0.2x to comply with the Full Scale range of the V-ADC. In addition there are three single ended
channels referenced to SGND. One channel is for measuring the internal temperature sensor
VPTAT and two channels for measuring the voltage at ADC0 and ADC1.
When the V-ADC is not used, power consumption can be minimized by writing the PRVADC bit
in PRR0 to one. See
the PRVADC bit.
Figure 20-1. Voltage ADC Block Schematic
To enable V-ADC conversions, the V-ADC Enable bit, VADEN, in V-ADC Control and Status
Register – VADCSR must be set. If this bit is cleared, the V-ADC will be switched off, and any
ongoing conversions will be terminated. The V-ADC is automatically disabled in Power-save and
12-bit Resolution
519µs Conversion Time @ 1 MHz clk
Two Differential Input Channels for Cell Voltage Measurements
Three Single Ended Input Channels
0.2x Pre-scaling of Cell Voltages
Interrupt on V-ADC Conversion Complete
VTEMP
ADC1
ADC0
PV2
PV1
NV
Note:
The shaded signals are scaled by 0.2,
other signals are scaled by 1.0
”PRR0 – Power Reduction Register 0” on page 39
INPUT
MUX
VADC
SIGMA-DELTA ADC
VREF
V-ADC MULTIPLEXER
8-BIT DATA BUS
V-ADC CONTROL
SEL. REG (VADMUX)
12-BIT
SGND
V-ADC CONVERSION COMPLETE IRQ
STATUS REG (VADCSR)
V-ADC DATA REGISTER
V-ADC CONTROL AND
(VADCL/ADCH)
for details on how to use
8024A–AVR–04/08