ATMEGA16HVA-4CKU Atmel, ATMEGA16HVA-4CKU Datasheet - Page 56

• Manufacturer Part Number: ATMEGA16HVA-4CKU
• Description: MCU AVR 16K FLASH 4MHZ 36-LGA
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16HVA-4CKU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 7
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 9 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-LGA
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200, ATAVRSB201
• Minimum Operating Temperature: - 20 C
• On-chip Adc: 12 bit, 5 Channel
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13. External Interrupts
13.1
13.2
13.2.1
56
Overview
Register Description
ATmega8HVA/16HVA
EICRA – External Interrupt Control Register A
The External Interrupts are triggered by the INT2:0 pins. Observe that, if enabled, the interrupts
will trigger even if the INT2:0 pins are configured as outputs. This feature provides a way of gen-
erating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or
a low level. This is set up as indicated in the specification for the External Interrupt Control Reg-
ister – EICRA. When the external interrupt is enabled and is configured as level triggered, the
interrupt will trigger as long as the pin is held low. Interrupts are detected asynchronously. This
implies that these interrupts can be used for waking the part also from sleep modes other than
Idle mode. The I/O clock is halted in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-save mode, the changed
level must be held for some time to wake up the MCU. This makes the MCU less sensitive to
noise. The changed level is sampled twice by the ULP Oscillator clock. The period of the ULP
Oscillator is 7.8 µs (nominal) at 25°C. The MCU will wake up if the input has the required level
during this sampling or if it is held until the end of the start-up time. The start-up time is defined
by the SUT fuses as described in
is sampled twice by the ULP Oscillator clock but disappears before the end of the start-up time,
the MCU will still wake up, but no interrupt will be generated. The required level must be held
long enough for the MCU to complete the wake up to trigger the level interrupt.
• Bits 7,6 – RES: Reserved Bits
These bits are reserved in the ATmega8HVA/16HVA, and will always read as zero.
• Bits 5:0 – ISC21, ISC20 - ISC01, ISC00: External Interrupt 2 - 0 Sense Control Bits
The External Interrupts 2 - 0 are activated by the external pins INT2:0 if the SREG I-flag and the
corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that
activate the interrupts are defined in
nously. Pulses on INT2:0 pins wider than the minimum pulse width given in
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an inter-
rupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur.
Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the
EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be
cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the
interrupt is re-enabled.
Bit
(0x69)
Read/Write
Initial Value
R
7
0
-
R
6
0
-
ISC21
”Clock Systems and their Distribution” on page
R/W
5
0
Table
ISC20
13-1. Edges on INT2..INT0 are registered asynchro-
R/W
4
0
ISC11
R/W
3
0
ISC10
R/W
2
0
ISC01
R/W
1
0
ISC00
R/W
Table 29-2
0
0
24. If the level
8024A–AVR–04/08
EICRA
will