ATMEGA16HVA-4CKU Atmel, ATMEGA16HVA-4CKU Datasheet - Page 60

MCU AVR 16K FLASH 4MHZ 36-LGA

ATMEGA16HVA-4CKU

Manufacturer Part Number
ATMEGA16HVA-4CKU
Description
MCU AVR 16K FLASH 4MHZ 36-LGA
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet

Specifications of ATMEGA16HVA-4CKU

Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
7
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 9 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 85°C
Package / Case
36-LGA
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200, ATAVRSB201
Minimum Operating Temperature
- 20 C
On-chip Adc
12 bit, 5 Channel
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
14.4
60
Alternate Port Functions
ATmega8HVA/16HVA
The High Voltage I/O has alternate port functions in addition to being general digital I/O.
14-3
overridden by alternate functions.
Figure 14-3. High Voltage Digital I/O
Note:
Table 14-1 on page 61
indexes from
generated internally in the modules having the alternate function.
shows how the port pin control signals from the simplified
1. WRx, RRx and RPx are common to all pins within the same port. clk
mon to all ports. All other signals are unique for each pin.
Figure 14-3
Pxn
PVOExn:
PVOVxn:
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
Pxn PORT VALUE OVERRIDE ENABLE
Pxn PORT VALUE OVERRIDE VALUE
summarizes the function of the overriding signals. The pin and port
are not shown in the succeeding tables. The overriding signals are
1
0
DIEOExn
DIEOVxn
(1)
SLEEP
1
0
SYNCHRONIZER
D
L
SET
CLR
RRx:
WRx:
RPx:
clk
DIxn:
SLEEP:
PVOExn
PVOVxn
Q
_
Q
I/O
:
D
PINxn
RESET
CLR
PORTxn
READ PORTx REGISTER
WRITE PORTx REGISTER
READ PINx REGISTER
I/O CLOCK
DIGITAL INPUT PIN n ON PORTx
SLEEP CONTROL
Q
Q
_
Q
Q
CLR
_
D
Figure 14-2 on page 59
clk
RRx
RPx
WRx
I/O
DIxn
I/O
and SLEEP are com-
8024A–AVR–04/08
can be
Figure

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