ATMEGA16HVA-4CKU Atmel, ATMEGA16HVA-4CKU Datasheet - Page 79

• Manufacturer Part Number: ATMEGA16HVA-4CKU
• Description: MCU AVR 16K FLASH 4MHZ 36-LGA
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16HVA-4CKU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 7
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 9 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-LGA
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200, ATAVRSB201
• Minimum Operating Temperature: - 20 C
• On-chip Adc: 12 bit, 5 Channel
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.4
8024A–AVR–04/08
Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
17-2 on page 79
Figure 17-2. Counter Unit Block Diagram
The counter is incremented at each timer clock (clk
restarts from BOTTOM. The counting sequence is determined by the setting of the WGMn0 bits
located in the Timer/Counter Control Register (TCCRnA). For more details about counting
sequences, see
external or internal clock source, selected by the Clock Select bits (CSn2:0). When no clock
source is selected (CSn2:0 = 0) the timer is stopped. However, the TCNTn value can be
accessed by the CPU, regardless of whether clk
priority over) all counter clear or count operations. The Timer/Counter Overflow Flag (TOVn) is
set when the counter reaches the maximum value and it can be used for generating a CPU
interrupt.
Signal description (internal signals):
count
clk
top
Tn
Increment or decrement TCNTn by 1.
Timer/Counter clock, referred to as clk
Signalize that TCNTn has reached maximum value.
”Timer/Counter Timing Diagrams” on page
shows a block diagram of the counter and its surroundings.
DATA BUS
TCNTn
count
Control Logic
Tn
top
is present or not. A CPU write overrides (has
Tn
Tn
TOVn
(Int.Req.)
clk
ATmega8HVA/16HVA
in the following.
) until it passes its TOP value and then
Tn
85. clk
Clock Select
( From Prescaler )
Detector
Edge
Tn
can be generated from an
Tn
Figure
79