ATMEGA16HVA-4CKU Atmel, ATMEGA16HVA-4CKU Datasheet - Page 132

• Manufacturer Part Number: ATMEGA16HVA-4CKU
• Description: MCU AVR 16K FLASH 4MHZ 36-LGA
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16HVA-4CKU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 7
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 9 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-LGA
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200, ATAVRSB201
• Minimum Operating Temperature: - 20 C
• On-chip Adc: 12 bit, 5 Channel
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.9.9
23.9.10
132
ATmega8HVA/16HVA
BPDHCD – Battery Protection Discharge-High-current Detection Level Register
BPCHCD – Battery Protection Charge-High-current Detection Level Register
• Bits 7:0 – DHCDL7:0: Discharge High-current Detection Level
These bits sets the R
Table 23-5 on page
Note:
• Bits 7:0 –CHCDL7:0: Charge High-current Detection Level
These bits sets the R
Table 23-5 on page
Note:
Table 23-5.
Bit
(0xF8)
Read/Write
Initial Value
Bit
(0xF9)
Read/Write
Initial Value
Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the BPDHCD register is written. Any
writing to the BPDHCD register during this period will be ignored.
Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the BPCHCD register is written. Any
writing to the BPCHCD register during this period will be ignored.
DL[7:0]
0xFB
0xFC
0xFD
0xF3
0xF4
0xF5
0xF6
0xF7
0xF8
0xF9
0xFA
DL[7:0] with corresponding R
(R
R/W
R/W
SENSE
7
1
7
1
132.
132.
SENSE
SENSE
= 10 mΩ, VREF = 1.100 ± 0.005V, T
R/W
R/W
6
1
6
1
voltage level for detection of Discharge High-current, as defined in
voltage level for detection of Charge High-current, as defined in
Current Protection Detection Level
Min.
R/W
R/W
5
1
5
1
R/W
R/W
SENSE
4
1
4
1
DHCDL[7:0]
CHCDL[7:0]
Current for all Current Detection Levels
R/W
R/W
3
0
3
0
Typ.
2.0A
2.5A
3.0A
3.5A
4.0A
4.5A
5.0A
5.5A
6.0A
6.5A
7.0A
A
= -10°C to 70°C)
R/W
R/W
2
0
2
0
R/W
R/W
1
1
1
1
R/W
R/W
0
1
0
1
Max.
8024A–AVR–04/08
BPDHCD
BPCHCD