ATMEGA16HVA-4CKU Atmel, ATMEGA16HVA-4CKU Datasheet - Page 147

• Manufacturer Part Number: ATMEGA16HVA-4CKU
• Description: MCU AVR 16K FLASH 4MHZ 36-LGA
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16HVA-4CKU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 7
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 9 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-LGA
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200, ATAVRSB201
• Minimum Operating Temperature: - 20 C
• On-chip Adc: 12 bit, 5 Channel
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26.3
26.3.1
8024A–AVR–04/08
Register Description
SPMCSR – Store Program Memory Control and Status Register
Table 26-4.
The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Program memory operations.
• Bits 7:6 – Res: Reserved Bits
These bits are reserved for future use.
For compatibility with future devices, these bits must be written to zero when SPMCSR is
written.
• Bit 5 – SIGRD: Signature Row Read
If this bit is written to one at the same time as SPMEN, the next LPM instruction within three
clock cycles will read a byte from the signature row into the destination register. See
the Signature Row from Software” on page 144
An SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect. This
operation is reserved for future use and should not be used.
• Bit 4 – CTPB: Clear Temporary Page Buffer
If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be
cleared and the data will be lost.
• Bit 3 – RFLB: Read Fuse and Lock Bits
An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register,
will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destina-
tion register. See
Bit
0x37 (0x57)
Read/Write
Initial Value
Variable
PAGEMSB
ZPCMSB
ZPAGEMSB
PCPAGE
PCWORD
Explanation of different variables used in
pointer, ATmega16HVA.
PC[12:6]
R
7
–
0
PC[5:0]
”EEPROM Write Prevents Writing to SPMCSR” on page 143
5
R
6
–
0
Corresponding
Z-value
Z13:Z7
Z6:Z1
SIGRD
R/W
Z13
Z6
5
0
CTPB
R/W
4
0
Description
Most significant bit which is used to address the
words within one page (64 words in a page requires
six bits PC [5:0]).
Bit in Z-register that is mapped to PCMSB. Because
Z0 is not used, the ZPCMSB equals PCMSB + 1.
Bit in Z-register that is mapped to PCMSB. Because
Z0 is not used, the ZPAGEMSB equals PAGEMSB +
1.
Program Counter page address: Page select, for
Page Erase and Page Write
Program Counter word address: Word select, for
filling temporary buffer (must be zero during Page
Write operation)
for details.
RFLB
R/W
3
0
ATmega8HVA/16HVA
Figure 26-1
PGWRT
R/W
2
0
and the mapping to the Z-
PGERS
R/W
1
0
for details.
SPMEN
R/W
0
0
”Reading
SPMCSR
147