ATMEGA16HVA-4CKU Atmel, ATMEGA16HVA-4CKU Datasheet - Page 138

• Manufacturer Part Number: ATMEGA16HVA-4CKU
• Description: MCU AVR 16K FLASH 4MHZ 36-LGA
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16HVA-4CKU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 7
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 9 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-LGA
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200, ATAVRSB201
• Minimum Operating Temperature: - 20 C
• On-chip Adc: 12 bit, 5 Channel
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.4
24.4.1
138
Register Description
ATmega8HVA/16HVA
FCSR – FET Control and Status Register
• Bits 7:4 – Res: Reserved Bits
These bits are reserved bits in the ATmega8HVA/16HVA, and will always read as zero.
• Bit 3 – DUVRD: Deep Under-voltage Recovery Disabled
When the DUVRD is cleared (zero), the FET Driver will be forced to operate in Deep Under-volt-
age Recovery DUVR mode. See
page 137
protection or during internal reset, the DUVRD bit is overridden to one by hardware in these
cases. When this bit is set (one), Deep Under-voltage Recovery mode of the FET Driver will be
disabled.
• Bit 2 – CPS: Current Protection Status
The CPS bit shows the status of the Current Protection. This bit is set (one) when a Current Pro-
tection is active, and cleared (zero) otherwise.
• Bit 1 – DFE: Discharge FET Enable
When the DFE bit is cleared (zero), the Discharge FET will be disabled regardless of the state of
the Battery Protection circuitry. When this bit is set (one), the Discharge FET is enabled. This bit
will automatically be cleared by the CBP circuitry when Current Protection is activated. When
this bit is cleared, Short-circuit, Discharge High-current and Discharge Over-current are disabled
regardless of the settings in the BPCR Register.
• Bit 0 – CFE: Charge FET Enable
When the CFE bit is cleared (zero), the Charge FET will be disabled regardless of the state of
the Battery Protection circuitry. When this bit is set (one), the Charge FET is enabled. This bit
will automatically be cleared by the CBP circuitry when Current Protection is activated. When
this bit is cleared and the DUVRD bit is set, Charge High-current Protection and Charge Over-
current Protection are disabled regardless of the settings in the BPCR Register. When the
DUVRD bit is cleared, the charge FET will be enabled by DUVR mode regardless of the CFE
status.
Note:
Bit
(0xF0)
Read/Write
Initial Value
Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the FCSR register is written. Any writ-
ing to the FCSR register during this period will be ignored.
for details. To avoid that the FET driver tries to switch on the C-FET during current
R
7
–
0
R
6
–
0
R
5
–
0
”DUVR – Deep Under-Voltage Recovery Mode operation” on
R
4
–
0
DUVRD
R/W
3
0
CPS
R
2
0
DFE
R/W
1
0
CFE
R/W
0
0
FCSR
8024A–AVR–04/08