ATMEGA16HVA-4CKU Atmel, ATMEGA16HVA-4CKU Datasheet - Page 64

• Manufacturer Part Number: ATMEGA16HVA-4CKU
• Description: MCU AVR 16K FLASH 4MHZ 36-LGA
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16HVA-4CKU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 7
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 9 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-LGA
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200, ATAVRSB201
• Minimum Operating Temperature: - 20 C
• On-chip Adc: 12 bit, 5 Channel
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.2
15.2.1
64
Low Voltage Ports as General Digital I/O
ATmega8HVA/16HVA
Configuring the Pin
Note that enabling the alternate function of some of the port pins does not affect the use of the
other pins in the port as general digital I/O.
The low voltage ports are bi-directional I/O ports with optional internal pull-ups.
shows a functional description of one I/O-port pin, here generically called Pxn.
Figure 15-2. General Low Voltage Digital I/O
Note:
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in
Description” on page
at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to
be configured as an output pin. The port pins are tri-stated when reset condition becomes active,
even if no clocks are running.
Pxn
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
SLEEP, and PUD are common to all ports.
PUD:
SLEEP:
clk
I/O
73, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits
:
PULLUP DISABLE
SLEEP CONTROL
I/O CLOCK
SLEEP
(1)
SYNCHRONIZER
WDx:
RDx:
WRx:
RRx:
RPx:
WPx:
D
L
Q
Q
D
PINxn
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
WRITE PINx REGISTER
Q
Q
RESET
RESET
PORTxn
Q
Q
Q
Q
DDxn
CLR
CLR
D
D
RRx
PUD
WDx
RDx
RPx
clk
1
0
I/O
WPx
WRx
8024A–AVR–04/08
Figure 15-2
”Register
I/O
,