HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 135
HD6417706F133
Manufacturer Part Number
HD6417706F133
Description
IC SUPERH MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417706F133V.pdf
(751 pages)
Specifications of HD6417706F133
Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
176-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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Manufacturer:
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All exceptions other than a reset are detected in the pipeline ID stage, and accepted on instruction
boundaries. However, an exception is not accepted between a delayed branch instruction and the
delay slot. A re-execution type exception detected in a delay slot is accepted before execution of
the delayed branch instruction. A completion type exception detected in a delayed branch
instruction or delay slot is accepted after execution of the delayed branch instruction. The delay
slot here refers to the next instruction after a delayed unconditional branch instruction, or the next
instruction when a delayed conditional branch instruction is true.
4.1.4
Table 4.2 lists the exception codes written to bits 11 to 0 of the EXPEVT register for reset or
general exceptions or the INTEVT and INTEVT2 registers for general interrupt requests to
identify each specific exception event. An additional exception register, the TRAPA (TRA)
register, is used to hold the 8-bit immediate data in an unconditional trap (TRAPA instruction).
Table 4.2
Exception Type
Reset
General exception events
Exception Codes
Exception Codes
Exception Event
Power-on reset
Manual reset
H-UDI reset
TLB miss/invalid exception (load)
TLB miss/invalid exception (store)
Initial page write exception
TLB protection exception (load)
TLB protection exception (store)
CPU Address error (load)
CPU Address error (store)
Unconditional trap (TRAPA instruction)
Reserved instruction code exception
Illegal slot instruction exception
User breakpoint trap
DMA address error
Rev. 5.00 May 29, 2006 page 85 of 698
Section 4 Exception Processing
H'1A0
Exception Code
H'000
H'020
H'000
H'040
H'060
H'080
H'0A0
H'0C0
H'0E0
H'100
H'160
H'180
H'1E0
H'5C0
REJ09B0146-0500
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