HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 30

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

9.7
Section 10 Clock Pulse Generator (CPG)
10.1 Feature .............................................................................................................................. 303
10.2 Input/Output Pin................................................................................................................ 306
10.3 Clock Operating Modes .................................................................................................... 306
10.4 Register Description.......................................................................................................... 310
10.5 Operation .......................................................................................................................... 312
10.6 Usage Note........................................................................................................................ 313
Section 11 Watchdog Timer (WDT)
11.1 Feature .............................................................................................................................. 315
11.2 Register Description.......................................................................................................... 316
11.3 Operation .......................................................................................................................... 319
Section 12 Timer Unit (TMU)
12.1 Feature .............................................................................................................................. 323
12.2 Input/Output Pin................................................................................................................ 325
12.3 Register Description.......................................................................................................... 325
12.4 Operation .......................................................................................................................... 332
12.5 Interrupts ........................................................................................................................... 337
Rev. 5.00 May 29, 2006 page xxviii of xlviii
9.6.2
Cautions ............................................................................................................................ 301
10.4.1 Frequency Control Register (FRQCR)................................................................. 310
10.5.1 Changing the Multiplication Rate ........................................................................ 312
10.5.2 Changing the Division Ratio................................................................................ 312
11.2.1 Watchdog Timer Counter (WTCNT)................................................................... 316
11.2.2 Watchdog Timer Control/Status Register (WTCSR)........................................... 316
11.2.3 Notes on Register Access..................................................................................... 318
11.3.1 Canceling Software Standbys .............................................................................. 319
11.3.2 Changing the Frequency ...................................................................................... 320
11.3.3 Using Watchdog Timer Mode.............................................................................. 320
11.3.4 Using Interval Timer Mode ................................................................................. 321
12.3.1 Timer Output Control Register (TOCR) .............................................................. 326
12.3.2 Timer Start Register (TSTR)................................................................................ 327
12.3.3 Timer Control Registers 0 to 2 (TCR_0 to TCR_2)............................................. 328
12.3.4 Timer Constant Registers 0 to 2 (TCOR_0 to TCOR_2)..................................... 331
12.3.5 Timer Counters 0 to 2 (TCNT_0 to TCNT_2)..................................................... 332
12.3.6 Input Capture Register 2 (TCPR_2)..................................................................... 332
12.4.1 Counter Operation................................................................................................ 333
12.4.2 Input Capture Function ........................................................................................ 336
Example of DMA Transfer between External Memory and SCIF Transmitter
(Indirect Address on) ........................................................................................... 299
......................................................................................... 323
.............................................................................. 315
..................................................................... 303