HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 632

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 22 Power-Down Modes
22.3.5
Transition to Hardware Standby Mode
Driving the CA pin low causes a transition to hardware standby mode. In hardware standby mode,
all modules except those operating on an RTC clock are halted, as in the software standby mode
entered on execution of a SLEEP instruction ((software) standby mode).
Hardware standby mode differs from software standby mode as follows.
1. Interrupts and manual resets are not accepted.
2. The TMU does not operate.
Operation when a low-level signal is input at the CA pin depends on the CPG state, as follows.
1. In software standby mode
2. During WDT operation when software standby mode is canceled by an interrupt
3. In sleep mode
Hold the CA pin low in hardware standby mode.
In hardware standby mode, the LSI can supply power only to the RTC power-supply pin.
Canceling Hardware Standby Mode
Hardware standby mode can only be canceled by a power-on reset.
When the CA pin is driven high while the RESETP pin is low, clock oscillation is started. Hold
the RESETP pin low until clock oscillation stabilizes. When the RESETP pin is driven high, the
CPU begins power-on reset processing.
If an interrupt or manual reset is input, correct operation cannot be guaranteed.
Rev. 5.00 May 29, 2006 page 582 of 698
REJ09B0146-0500
The clock remains stopped and the chip enters the hardware standby state. Acceptance of
interrupts and manual resets is disabled, TCLK output is fixed low, and the TMU halts.
The chip enters hardware standby mode after standby mode is canceled and the CPU resumes
operation.
The chip enters hardware standby mode after sleep mode is canceled and the CPU resumes
operation.
Hardware Standby Function