HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 455

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

In transmitting serial data, the SCI operates as follows:
1. The SCI monitors the TDRE bit in the SCSSR. When TDRE is cleared to 0 the SCI recognizes
2. After loading the data from the SCTDR into the SCTSR, the SCI sets the TDRE bit to 1 and
3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads data
Figure 14.14 shows SCI transmission in the multiprocessor format.
that the SCTDR contains new data, and loads this data from the SCTDR into the SCTSR.
starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCSCR is set to
1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is
transmitted in the following order from the TxD0 pin:
a. Start bit: One 0 bit is output.
b. Transmit data: Seven or eight bits are output, LSB first.
c. Multiprocessor bit: One multiprocessor bit (MPBT value) is output.
d. Stop bit: One or two 1 bits (stop bits) are output.
e. Marking: Output of 1 bits continues until the start bit of the next transmit data.
from the SCTDR into the SCTSR, outputs the stop bit, then begins serial transmission of the
next frame. If TDRE is 1, the SCI sets the TEND bit in the SCSSR to 1, outputs the stop bit,
then continues output of 1 bits in the marking state. If the transmit-end interrupt enable bit
(TEIE) in the SCSCR is set to 1, a transmit-end interrupt (TEI) is requested at this time.
Section 14 Serial Communication Interface (SCI)
Rev. 5.00 May 29, 2006 page 405 of 698
REJ09B0146-0500