HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 516

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.9
The FIFO control register 2 (SCFCR2) resets the number of data in the SCFTDR2 and SCFRDR2,
sets the number of trigger data, and contains an enable bit for the loop back test. The SCFCR2 is
always read and written by the CPU.
Bit
7
6
5
4
3
Rev. 5.00 May 29, 2006 page 466 of 698
REJ09B0146-0500
Bit Name
RTRG1
RTRG0
TTRG1
TTRG0
MCE
FIFO Control Register 2 (SCFCR2)
Initial
Value
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Trigger of the Number of Receive FIFO Data
Set the reference number of the receive data full.
The RDF in SCSSR2 is set to 1, when the receiving data
count has exceeded the following trigger number.
00:
01:
10:
11:
Trigger of the Number of Transmit FIFO Data
Set the reference number of the send data empty. The
TDFE in SCSSR2 is set to 1, when the transmitting data
count has fallen the following trigger number.
00:
01:
10:
11:
Note: Values in brackets mean the number of empty bytes
Modem Control Enable
Enables the modem control signals CTS2 and RTS2.
0: Disables the modem signal *
1: Enables the modem signal
Note: * The CTS2 is fixed to active 0 regardless of the
Trigger number of receive data.
Trigger number of transmit data.
in SCFTDR when the TDFE is set.
input value, and the RTS2 is also fixed to 0.
1
4
8
14
8 (8)
4 (12)
2 (14)
1 (15)