HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 591

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Typical operations when three channels in group 0 (AN0 to AN2) are selected in scan mode are
described next. Figure 19.6 shows a timing diagram for this example.
1. Multi mode is selected (MULTI = 1, SCN = 0), channel group 0 is selected (CH2 = 0), analog
2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into
3. Conversion proceeds in the same way through the third channel (AN2).
4. When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1
When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1,
A/D conversion starts again from the first channel (AN0).
Channel 0 (AN0)
Channel 1 (AN1)
Channel 2 (AN2)
Channel 3 (AN3)
input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started
(ADST = 1).
ADDRA. Next, conversion of the second channel (AN1) starts automatically.
and ADST bit is cleared to 0. If the ADIE bit is set to 1, an ADI interrupt is requested at this
time.
operating
operating
operating
operating
ADDRC
ADDRD
ADDRA
ADDRB
ADST
ADF
Figure 19.6 Example of A/D Converter Operation (Multi Mode,
Note: * Downward arrows ( ) indicate instruction executed by software.
Waiting
Waiting
Waiting
Waiting
A/D conversion 1
Channels AN0 to AN2 Selected)
Set *
A/D conversion 2
A/D conversion
Transfer
A/D conversion 3
A/D conversion result 1
Waiting
Rev. 5.00 May 29, 2006 page 541 of 698
Waiting
Clear *
Section 19 A/D Converter (ADC)
A/D conversion result 2
A/D conversion result 3
Waiting
REJ09B0146-0500
Clear *