HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 69

IC SUPERH MPU ROMLESS 176LQFP

HD6417706F133

Manufacturer Part Number
HD6417706F133
Description
IC SUPERH MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417706F133

Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
176-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

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Note: The M, Q, S and T bits can be set or cleared by special instructions in user mode. Their
Bit
11, 10
9
8
7
6
5
4
3, 2
1
0
Saved Status Register (SSR)
Stores current SR value at time of exception to indicate processor status in return to instruction
stream from exception handler.
Initialized to undefined by a reset.
Saved Program Counter (SPC)
Stores current PC value at time of exception to indicate return address at completion of
exception handling.
Initialized to undefined by a reset.
values are undefined after a reset. All other bits can be read or written in privileged mode.
Bit Name
M
Q
I3
I2
I1
I0
S
T
Initial Value
All 0
1
1
1
1
All 0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
Description
Reserved
These bits always read as 0, and the write value
should always be 0.
M bit
Q bit
Used by the DIV0S/U and DIV1 instructions.
Interrupt mask bits
4-bit field indicating the interrupt request mask
level.
I3 to I0 do not change to the interrupt
acceptance level when an interrupt is occurred.
Reserved
These bits always read as 0, and the write value
should always be 0.
S bit
Used by the MAC instruction.
T bit
Used by the MOVT, CMP/cond, TAS, TST, BT,
BF, SETT, CLRT, and DT instructions to
indicate true (1) or false (0).
Used by the ADDV/C, SUBV/C, DIV0U/S, DIV1,
NEGC, SHAR/L, SHLR/L, ROTR/L, and
ROTCR/L instructions to indicate a carry,
borrow, overflow, or underflow.
Rev. 5.00 May 29, 2006 page 19 of 698
REJ09B0146-0500
Section 2 CPU

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