HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 532
HD6417706F133
Manufacturer Part Number
HD6417706F133
Description
IC SUPERH MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417706F133V.pdf
(751 pages)
Specifications of HD6417706F133
Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
176-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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Section 16 Serial Communication Interface with FIFO (SCIF)
5.
6.
The receive margin in asynchronous mode can therefore be expressed as shown in equation 1.
Equation 1:
Rev. 5.00 May 29, 2006 page 482 of 698
REJ09B0146-0500
Base clock
Receive data
(RxD2)
Synchronization
sampling timing
Data sampling
timing
TEND Flag and TE Bit Processing
The TEND flag is set to 1 during transmission of the stop bit of the last data. Consequently, if
the TE bit is cleared to 0 immediately after setting of the TEND flag has been confirmed, the
stop bit will be in the process of transmission and will not be transmitted normally. Therefore,
the TE bit should not be cleared to 0 for at least 0.5 serial clock cycles (or 1.5 cycles if two
stop bits are used) after setting of the TEND flag setting is confirmed.
Receive Data Sampling Timing and Receive Margin
The SCIF operates on a base clock with a frequency of 16 times the transfer rate. In reception,
the SCIF synchronizes internally with the fall of the start bit, which it samples on the base
clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is
shown in figure 16.13.
M = 0.5 –
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
Figure 16.13 Receive Data Sampling Timing in Asynchronous Mode
0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5
2N
1
8 clocks
Start bit
– (L – 0.5) F –
16 clocks
–7.5 clocks
D – 0.5
N
(1 + F)
+7.5 clocks
100%
D0
D1
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