HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 419
HD6417706F133
Manufacturer Part Number
HD6417706F133
Description
IC SUPERH MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417706F133V.pdf
(751 pages)
Specifications of HD6417706F133
Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
176-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Price
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Quantity:
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Part Number:
HD6417706F133V
Manufacturer:
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Quantity:
20 000
- Current page: 419 of 751
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14.3.5
The serial mode register (SCSMR) is an eight-bit register that specifies the SCI serial
communication format and selects the clock source for the baud rate generator.
The CPU can always read and write the SCSMR.
Bit
7
6
5
Bit Name
C/A
CHR
PE
Serial Mode Register (SCSMR)
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Communication Mode
Selects whether the SCI operates in the
asynchronous or clock synchronous mode.
0: Asynchronous mode
1: Clock synchronous mode
Character Length
Selects seven-bit or eight-bit data length in the
asynchronous mode. In the clock synchronous
mode, the data length is always eight bits,
regardless of the CHR setting.
0: Eight-bit data
1: Seven-bit data
Parity Enable
Selects whether to add a parity bit to the transmit
data or to check the parity of receive data in
asynchronous mode. In the clock synchronous
mode, a parity bit is neither added nor checked,
regardless of the PE setting.
0: Parity bit not added and not checked
1: Parity bit added and checked
Description
Section 14 Serial Communication Interface (SCI)
Note: When PE is set to 1, an even or odd
parity bit is added to transmit data, depending
on the parity mode (O/E) setting. Receive data
parity is checked according to the even/odd
(O/E) mode setting.
Note: When seven-bit data is selected, the
MSB (bit 7) in the SCTDR is not transmitted.
Rev. 5.00 May 29, 2006 page 369 of 698
REJ09B0146-0500
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