HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 215

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

8.2
Table 8.1 lists the BSC pin configuration.
Table 8.1
Pin Name
Address bus
Data bus
Bus cycle start
Chip select 0, 2 to 4
Chip select 5, 6
PCMCIA card
select
Read/write
Row address strobe
L
Row address strobe
U
Column address
strobe
Column address
strobe
Data enable 0
Data enable 1
Input/Output Pin
Pin Configuration
Signal
A25 to A0
D15 to D0
D31 to D16
BS
CS0, CS2 to
CS4
CS5/CE1A,
CS6/CE1B
CE2A, CE2B
RD/WR
RASL
RASU
CASL
CASU
WE0/DQMLL
WE1/DQMLU/
WE
I/O
O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
Description
Address output
Data I/O
When 32-bit bus width, data I/O
Shows start of bus cycle. During burst transfers,
asserts every data cycle.
Chip select signal to indicate area being accessed.
Chip select signal to indicate area being accessed.
CS5/CE1A and CS6/CE1B can also be used as
CE1A and CE1B of PCMCIA.
When PCMCIA is used, CE2A and CE2B
Data bus direction indicator signal. Synchronous
DRAM write indicator signal.
When synchronous DRAM is used, RASL for
lower 32-Mbyte address.
When synchronous DRAM is used, RASU for
upper 32-Mbyte address.
When synchronous DRAM is used, CASL signal
for lower 32-Mbyte address.
When synchronous DRAM is used, CASU signal
for upper 32-Mbyte address.
When memory other than synchronous DRAM is
used, selects D7 to D0 write strobe signal. When
synchronous DRAM is used, selects D7 to D0.
When memory other than synchronous DRAM is
used, selects D15 to D8 write strobe signal. When
synchronous DRAM is used, selects D15 to D8.
When PCMCIA is used, strobe signal that
indicates the write cycle.
Rev. 5.00 May 29, 2006 page 165 of 698
Section 8 Bus State Controller (BSC)
REJ09B0146-0500