HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 236

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 8 Bus State Controller (BSC)
8.4.5
The individual memory control register (MCR) is a 16-bit read/write register that specifies RAS
and CAS timing and burst control for synchronous DRAM (areas 2 and 3), specifies address
multiplexing, and controls refresh. This enables direct connection of synchronous DRAM without
external circuits.
The MCR is initialized to H'0000 by power-on resets, but is not initialized by manual resets or
standby mode. The bits TPC1, TPC0, RCD1, RCD0, TRWL1, TRWL0, TRAS1, TRAS0, RASD
and AMX3 to AMX0 are written to at the initialization after a power-on reset and are not then
modified again. When RFSH and RMODE are written to, write the same values to the other bits.
When using synchronous DRAM, do not access areas 2 and 3 until this register is initialized.
Rev. 5.00 May 29, 2006 page 186 of 698
REJ09B0146-0500
Bit
15
14
Bit Name
TPC1
TPC0
Individual Memory Control Register (MCR)
Initial Value
0
0
R/W
R/W
R/W
Description
RAS Precharge Time
When synchronous DRAM interface is selected as
connected memory, they set the minimum number of
cycles until output of the next bank-active command
after precharge.
The number of cycles to be inserted immediately
after issuing a precharge all banks (PALL) command
in auto-refresh or a precharge (PRE) command in
bank-active mode is one cycle less than the normal
value. In bank-active mode, neither TPC1 nor TPC0
should be cleared to 0.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
Note: * Immediately after a precharge all banks (PALL)
Normal
Operation
command in auto-refresh and a precharge (PRE)
command in bank-active mode.
Immediately after * Immediately
Precharge
Command
0 cycle
1 cycle
2 cycles
3 cycles
after
Self-Refresh
2 cycles
5 cycles
8 cycles
11 cycles