HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 25

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 1 Overview
1.1
1.2
1.3
1.4
Section 2 CPU
2.1
2.2
2.3
2.4
2.5
Section 3 Memory Management Unit (MMU)
3.1
3.2
3.3
Feature ..............................................................................................................................
Block Diagram ..................................................................................................................
Pin Assignment .................................................................................................................
Pin Function ......................................................................................................................
Register Description.......................................................................................................... 13
2.1.1
2.1.2
2.1.3
2.1.4
Data Formats..................................................................................................................... 20
2.2.1
2.2.2
Instruction Features........................................................................................................... 21
2.3.1
2.3.2
2.3.3
Instruction Set ................................................................................................................... 30
2.4.1
2.4.2
Processor States and Processor Modes.............................................................................. 49
2.5.1
2.5.2
Role of MMU.................................................................................................................... 51
3.1.1
Register Description.......................................................................................................... 56
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
TLB Functions .................................................................................................................. 60
3.3.1
3.3.2
Privileged Mode and Banks ................................................................................. 13
General Registers ................................................................................................. 15
System Registers.................................................................................................. 16
Control Registers ................................................................................................. 17
Data Format in Registers...................................................................................... 20
Data Format in Memory....................................................................................... 20
Execution Environment ....................................................................................... 21
Addressing Modes ............................................................................................... 23
Instruction Formats .............................................................................................. 27
Instruction Set Classified by Function ................................................................. 30
Instruction Code Map .......................................................................................... 46
Processor States ................................................................................................... 49
Processor Modes .................................................................................................. 50
This LSI's MMU .................................................................................................. 53
Page Table Entry Register High (PTEH) ............................................................. 57
Page Table Entry Register Low (PTEL) .............................................................. 57
The Translation Table Base Register (TTB) ........................................................ 58
The TLB Exception Address Register (TEA) ...................................................... 58
MMU Control Register (MMUCR) ..................................................................... 58
Configuration of the TLB .................................................................................... 60
TLB Indexing....................................................................................................... 62
...................................................................................................................... 13
.............................................................................................................
Contents
Rev. 5.00 May 29, 2006 page xxiii of xlviii
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