HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 335
HD6417706F133
Manufacturer Part Number
HD6417706F133
Description
IC SUPERH MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417706F133V.pdf
(751 pages)
Specifications of HD6417706F133
Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
176-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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Section 9 Direct Memory Access Controller (DMAC)
Operation
Cycle-Steal Mode
In the cycle-steal mode, the DREQ sampling timing is the same regardless of whether level or
edge detection is used.
For example, in figure 9.17 (cycle-steal mode, level detection), DMAC transfer begins, at the
earliest, three cycles after the first sampling is performed. The second sampling is started two
cycles after the first. If DREQ is not detected at this time, sampling is performed in each
subsequent cycle.
Thus, DREQ sampling is performed one step in advance. The third sampling operation is not
performed until the idle cycle following the end of the first DMA transfer.
The above conditions are the same whatever the number of CPU transfer cycles, as shown in
figure 9.18, and whatever the number of DMA transfer cycles, as shown in figure 9.19.
DACK is output in a read in the example in figure 9.17, and in a write in the example in figure
9.18. In both cases, DACK is output for the same duration as CSn.
Figure 9.20 illustrates the case where DREQ is not detected and sampling is subsequently
executed every cycle.
Figure 9.21 shows an example of edge detection in the cycle-steal mode.
Burst Mode, Level Detection
In the case of burst mode with level detection, the DREQ sampling timing is the same as in the
cycle-steal mode.
For example, in figure 9.22, DMAC transfer begins, at the earliest, three cycles after the first
sampling is performed. The second sampling is started two cycles after the first. Subsequent
sampling operations are performed in the idle cycle following the end of the DMA transfer
cycle.
In the burst mode, also, the DACK output period is the same as in the cycle-steal mode.
Burst Mode, Edge Detection
In the case of burst mode with edge detection, DREQ sampling is only performed once.
For example, in figure 9.23, DMAC transfer begins, at the earliest, three cycles after the first
sampling is performed. After this, DMAC transfer is executed continuously until the number
of data transfers set in the DMATCR register have been completed. DREQ is not sampled
during this time.
To restart DMA transfer after it has been suspended by an NMI, first clear NMIF, then input
an edge request again.
In the burst mode, also, the DACK output period is the same as in the cycle-steal mode.
Rev. 5.00 May 29, 2006 page 285 of 698
REJ09B0146-0500
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