HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 521

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 16 Serial Communication Interface with FIFO (SCIF)
Clock
An internal clock generated by the on-chip baud rate generator or an external clock input from the
SCK2 pin can be selected as the SCIF transmit/receive clock. The clock source is selected by bits
CKE1 and CKE0 in the serial control register (SCSCR2) (table 16.7).
When an external clock is input at the SCK2 pin, it must have a frequency equal to 16 times the
desired bit rate.
When the SCIF operates on an internal clock, it can output a clock signal at the SCK2 pin. The
frequency of this output clock is 16 times the bit rate.
Transmitting and Receiving Data (SCIF Initialization)
Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register
(SCSCR2), then initialize the SCIF as follows.
When changing the communication format, always clear the TE and RE bits to 0 before following
the procedure given below. Clearing TE to 0 initializes the transmit shift register (SCTSR2).
Clearing TE and RE to 0, however, does not initialize the serial status register (SCSSR2), transmit
FIFO data register (SCFTDR2), or receive FIFO data register (SCFRDR2), which retain their
previous contents. Clear TE to 0 after all transmit data are transmitted and the TEND flag in the
SCSSR2 is set. The transmitting data enters the high impedance state after clearing to 0 although
the bit can be cleared to 0 in transmitting. Set the TFRST bit in the SCFCR2 to 1 and reset the
SCFTDR2 before TE is set again to start transmission.
When an external clock is used, the clock should not be stopped during initialization or subsequent
operation. SCIF operation becomes unreliable if the clock is stopped.
Figure 16.5 is a sample flowchart for initializing the SCIF. The procedure for initializing the SCIF
is:
Rev. 5.00 May 29, 2006 page 471 of 698
REJ09B0146-0500