HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 263
HD6417706F133
Manufacturer Part Number
HD6417706F133
Description
IC SUPERH MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417706F133V.pdf
(751 pages)
Specifications of HD6417706F133
Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
176-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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Address Multiplexing
Synchronous DRAM can be connected without external multiplexing circuitry in accordance with
the address multiplex specification bits AMX3-AMX0 in MCR. Table 8.17 shows the relationship
between the address multiplex specification bits and the bits output at the address pins.
A25 to A17 and A0 are not multiplexed; the original values are always output at these pins.
When A0, the LSB of the synchronous DRAM address, is connected to this LSI, it performs
longword address specification. Connection should therefore be made in the following order:
connect pin A0 of the synchronous DRAM to pin A2 of this LSI, then connect pin A1 to pin A3.
Table 8.18 shows an example of the connection of address pins when AMX[3:0] = 0100 with 32-
bit bus width.
Figure 8.12 Example of 64-Mbit Synchronous DRAM (16-Bit Bus Width)
This LSI
DQMLU
RD/WR
DQMLL
RASx
CASx
CKIO
CKE
CSn
D15
A14
A13
A12
D0
A1
Rev. 5.00 May 29, 2006 page 213 of 698
Section 8 Bus State Controller (BSC)
64M synchronous DRAM
1M
A13
A12
A11
A0
CLK
CKE
CS
RAS
CAS
WE
DQ15
DQ0
DQMU
DQML
REJ09B0146-0500
16-bit
4-bank
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