HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 232

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 8 Bus State Controller (BSC)
8.4.4
Wait state control register 2 (WCR2) is a 16-bit read/write register that specifies the number of
wait state cycles inserted for each area. It also specifies the pitch of data access for burst memory
accesses. This allows direct connection of even low-speed memories without an external circuit.
Rev. 5.00 May 29, 2006 page 182 of 698
REJ09B0146-0500
Bit
15
14
13
12
11
10
9
8
7
6
5
Bit Name
A6W2
A6W1
A6W0
A5W2
A5W1
A5W0
A4W2
A4W1
A4W0
A3W1
A3W0
Wait State Control Register 2 (WCR2)
Initial Value R/W
1
1
1
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Area 6 Wait Control
Specify the number of wait states inserted into
physical space area 6 in combination with A6W3 in
PCR. Also specify the burst pitch for burst transfer.
Refer to table 8.6 for details.
Area 5 Wait Control
Specify the number of wait states inserted into
physical space area 5 in combination with A5W3 in
PCR. Also specify the burst pitch for burst transfer.
Refer to table 8.7 for details.
Area 4 Wait Control
Specify the number of wait states inserted into
physical space area 4.
Refer to table 8.8 for details.
Area 3 Wait Control
Specify the number of wait states inserted into
physical space area 3.
00:
01:
10:
11:
00:
01:
10:
11:
For Ordinary memory
For Synchronus DRAM
Inserted Wait States
Synchronus DRAM: CAS Latency
0
1
2
3
1
1
2
3
WAIT Pin
Ignored
Enable
Enable
Enable