HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 368

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 11 Watchdog Timer (WDT)
Note: The watchdog timer control/status register (WTCSR) is more difficult to write to than other
11.2.3
The WTCNT and WTCSR are more difficult to write to than other registers. The procedure for
writing to these registers are given below.
Writing to WTCNT and WTCSR: These registers must be written by a word transfer
instruction. They cannot be written by a byte or longword transfer instruction. When writing to
WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in
figure 11.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as
the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR.
Rev. 5.00 May 29, 2006 page 318 of 698
REJ09B0146-0500
Bit
2 to 0
registers to prevent from the erroneous writing to the register. Refer to 11.2.3, Notes on
Register Access.
Bit Name
CKS2 to
CKS0
Notes on Register Access
Initial Value R/W
0
R/W
Description
Clock Select 2 to 0
These bits select the clock to be used for the WTCNT
count from the eight types obtainable by dividing the
peripheral clock. The overflow period in the table is
the value when the peripheral clock (P ) is 15 MHz.
000: 1
001: 1/4
010: 1/16
011: 1/32
100: 1/64
101: 1/256
110: 1/1024
111: 1/4096
Note: If bits CKS2 to CKS0 are modified when the
Clock Division Ratio Overflow Period
WDT is running, the up-count may not be
performed correctly. Ensure that these bits are
modified only when the WDT is not running.
17 s
(when P = 15 MHz)
68 s
273 s
546 s
1.09 ms
4.36 ms
17.48 ms
69.91 ms