HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 614

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 21 User Debugging Interface (H-UDI)
21.5
Boundary Scan
A command can be set in SDIR by the H-UDI to place the H-UDI pins in the boundary scan mode
stipulated by JTAG.
21.5.1
Supported Instructions
This LSI supports the three essential instructions defined in the JTAG standard (BYPASS,
SAMPLE/PRELOAD, and EXTEST).
BYPASS: The BYPASS instruction is an essential standard instruction that operates the bypass
register. This instruction shortens the shift path to speed up serial data transfer involving other
chips on the printed circuit board. While this instruction is executing, the test circuit has no effect
on the system circuits. The instruction code is 1111.
SAMPLE/PRELOAD: The SAMPLE/PRELOAD instruction inputs values from this LSI's
internal circuitry to the boundary scan register, outputs values from the scan path, and loads data
onto the scan path. When this instruction is executing, this LSI's input pin signals are transmitted
directly to the internal circuitry, and internal circuit values are directly output externally from the
output pins. This LSI's system circuits are not affected by execution of this instruction. The
instruction code is 0100.
In a SAMPLE operation, a snapshot of a value to be transferred from an input pin to the internal
circuitry, or a value to be transferred from the internal circuitry to an output pin, is latched into the
boundary scan register and read from the scan path. Snapshot latching is performed in
synchronization with the rise of TCK in the Capture-DR state. Snapshot latching does not affect
normal operation of this LSI.
In a PRELOAD operation, an initial value is set in the parallel output latch of the boundary scan
register from the scan path prior to the EXTEST instruction. Without a PRELOAD operation,
when the EXTEST instruction was executed an undefined value would be output from the output
pin until completion of the initial scan sequence (transfer to the output latch) (with the EXTEST
instruction, the parallel output latch value is constantly output to the output pin).
EXTEST: This instruction is provided to test external circuitry when this LSI is mounted on a
printed circuit board. When this instruction is executed, output pins are used to output test data
(previously set by the SAMPLE/PRELOAD instruction) from the boundary scan register to the
printed circuit board, and input pins are used to latch test results into the boundary scan register
from the printed circuit board. If testing is carried out by using the EXTEST instruction N times,
the Nth test data is scanned-in when test data (N-1) is scanned out.
Rev. 5.00 May 29, 2006 page 564 of 698
REJ09B0146-0500