HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 205

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

3. When the data value is included in the break conditions on B channel:
4. When the DMAC data access is included in the break condition:
7.3.4
1. By specifying SEQ in BRCR is set to 1, the sequential break is issued when channel B break
2. In sequential break specification, logical or internal bus can be selected and the execution
7.3.5
The PC when a break occurs is saved to the SPC in user breaks. The PC value saved is as follows
depending on the type of break.
1. When instruction fetch (before instruction execution) is specified as a break condition:
Longword access at H'00001000
Word access at H'00001002
Byte access at H'00001003
When the data value is included in the break conditions, either longword, word, or byte is
specified as the operand size of the break bus cycle registers (BBRA and BBRB). When data
values are included in break conditions, a break is generated when the address conditions and
data conditions both match. To specify byte data for this case, set the same data in two bytes at
bits 15 to 8 and bits 7 to 0 of the break data register B (BDRB) and break data mask register B
(BDMRB). When word or byte is set, bits 31 to 16 of BDRB and BDMRB are ignored.
When the address is included in the break condition on DMAC data access, the operand size of
the break bus cycle registers (BBRA and BBRB) should be byte, word or no specified operand
size. When the data value is included, select either byte or word.
condition matches after channel A break condition matches. A user break is ignored even if
channel B break condition matches before channel A break condition matches. When channels
A and B condition match at the same time, the sequential break is not issued.
times break condition can be also specified. For example, when the execution times break
condition is specified, the break condition is satisfied at channel B condition match with BETR
= H'0001 after channel A condition match.
The value of the program counter (PC) saved is the address of the instruction that matches the
break condition. The fetched instruction is not executed, and a break occurs before it.
Sequential Break
Value of Saved Program Counter
Rev. 5.00 May 29, 2006 page 155 of 698
Section 7 User Break Controller
REJ09B0146-0500