WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 100

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

9.0
9.1
9.2
93
Non-Volatile Memory (NVM)
Introduction
This section is intended for designs using a 10/100/1000 Mb/s MAC that is integrated
into an Intel
Transceiver (PHY).
There are several LAN clients that might access the NVM such as hardware, LAN driver,
and BIOS. Refer to the Intel
Specification (Intel
Chipset SPI Programming Guide for more details.
Unless otherwise specified, all numbers in this section use the following numbering
convention:
NVM Programming Procedure Overview
The LAN NVM shares space on an SPI Flash device (or devices) along with the BIOS,
Manageability Firmware, and a Flash Descriptor Region. It is programmed through the
Intel
Descriptor Region is used to define vendor specific information and the location,
allocated space, and read and write permissions for each region. The Manageability
(ME) Region contains the code and configuration data for ME functions such as Intel
Active Management Technology. The system BIOS is contained in the BIOS Region. The
ME Region and BIOS Region are beyond the scope of this document and a more
detailed explanation of these areas can be found in the Intel
Family External Design Specification (Intel
document describes the LAN image contained in the Gigabit Ethernet (GbE) region.
• Numbers that do not have a suffix are decimal (base 10).
• Numbers with a prefix of “0x” are hexadecimal (base 16).
• Numbers with a suffix of “b” are binary (base 2).
®
5 Series Express Chipset. This combined image is shown in
®
5 Series Express Chipset in conjunction with an the 82577 Physical Layer
®
5 Series Express Chipset EDS) and the Intel
®
5 Series Express Chipset Family External Design
®
5 Series Express Chipset EDS). This
82577 GbE PHY—Non-Volatile Memory (NVM)
®
5 Series Express Chipset
®
Figure
5 Series Express
10. The Flash
®