WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 170

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

10.2.1.5
10.2.1.5.1
163
Power Management Register Descriptions
Wake Up Control Register - WUC (0x05800; RW)
The PME_Status bits are cleared in the following conditions:
0
1
2
3
4
5
7:6
8
29:9
31:30
• If there is VAUX, then the PME Status bits should be cleared by:
• If there is NO VAUX, then the PME Status bits should be cleared by:
Bits
— LAN_RST# or PCI reset
— Explicit software clear
— LAN_RST# or PCI reset
— PCI reset de-assertion
— Explicit software clear
RW/
SN
RW/V
RWC
RW
RW/
SN
RW/
SN
RO
RW/
SN
RO
RO
Type
0b
0b
0b
0b
0b
00b
0b
0x0
00b
1b
Reset
82577 GbE PHY—Intel
Advance Power Management Enable (APME).
1b = APM Wakeup is enabled.
0b = APM Wakeup is disabled.
Loaded from the NVM word 0x0A.
PME_En. This read/write bit is used by the driver to access the PME_En bit of the
Power Management Control / Status Register (PMCSR) without writing to PCI
configuration space.
PME_Status. This bit is set when the MAC receives a wake-up event. It is the same
as the PME_Status bit in the PMCSR. Writing a 1b to this bit clears it, and also
clears the PME_Status bit in the PMCSR.
Assert PME On APM Wakeup (APMPME). If set to 1b, the MAC sets the PMCSR and
asserts Host_Wake when APM wake up is enabled and the MAC receives a
matching magic packet.
Link Status Change Wake Enable (LSCWE). Enables wake on link status change as
part of APM wake capabilities.
Link Status Change Wake Override (LSCWO). If set to 1b, wake on link status
change does not depend on the LNKC bit in the Wake Up Filter Control (WUFC)
register. Instead, it is determined by the APM settings in the WUC register.
Reserved.
Phy_Wake. This bit indicates if the 82577 connected to the MAC supports wake up.
This bit is loaded from NVM word 0x13, bit 8.
Reserved. Reads as 0.
Reserved.
®
5 Series Express Chipset MAC Programming Interface
Description