WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 164

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Note:
10.2.1.4.2
157
Wire speeds of 1000 Mb/s result in a very short collision radius with traditional
minimum packet sizes. COLD specifies the minimum number of bytes in the packet to
satisfy the desired collision distance. It is important to note that the resulting packet
has special characters appended to the end. These are NOT regular data characters.
Hardware strips special characters for packets that go from 1000 Mb/s environments to
100 Mb/s environments. Note that hardware evaluates this field against the packet size
in full duplex as well.
While 802.3x flow control is only defined during full-duplex operation, the sending of
PAUSE frames via the SWXOFF bit is not gated by the duplex settings within the MAC.
Software should not write a 1b to this bit while the MAC is configured for half-duplex
operation.
RTLC configures the MAC to perform re-transmission of packets when a late collision is
detected.
10/100 Mb/s and 512 bytes for 1000 Mb/s operation. If a late collision is detected when
this bit is disabled, the transmit function assumes the packet is successfully
transmitted. This bit is ignored in full-duplex mode.
Transmit IPG Register - TIPG (0x00410; RW)
This register controls the Inter Packet Gap (IPG) timer. IPGT specifies the IPG length for
back-to-back transmissions in both full and half duplex. Note that an offset of 4-byte
times is added to the programmed value to determine the total IPG. Therefore, a value
of eight is recommended to achieve a 12-byte time IPG.
IPGR1 specifies the portion of the IPG in which the transmitter defers to receive events.
This should be set to 2/3 of the total effective IPG, or eight.
IPGR specifies the total IPG time for non back-to-back transmissions (transmission
following deferral) in half duplex.
An offset of 5-byte times is added to the programmed value to determine the total IPG
after a defer event. Therefore, a value of seven is recommended to achieve a 12-byte
time effective IPG for this case. Note the IPGR should never be set to a value greater
than IPGT. If IPGR is set to a value equal to or larger than IPGT, it overrides the IPGT
IPG setting in half duplex, resulting in inter packet gaps that are larger than intended
by IPGT in that case. Full duplex is unaffected by this, and always relies on IPGT only.
In summary, the recommended TIPG value to achieve 802.3 compliant minimum
transmit IPG values in full and half duplex is 0x00702008.
9:0
19:10
29:20
31:30
Bits
RW
RW
RW
RO
Type
Note that the collision window is speed dependent: 64 bytes for
0x8
0x8
0x9
00b
Reset
82577 GbE PHY—Intel
IPG Transmit Time (IPGT). Specifies the IPG length for back-to-back transmissions
equal to [(IPGT+4) x 8] bit time.
IPG Receive Time 1 (IPGR1). Specifies the defer IPG part 1 (during which carrier
sense is monitored). Equal to (IPGR1 x 8) when DJHDX=0 and equals to
(IPGR1+2) x 8 when DJHDX=1.
IPG Receive Time 2 (IPGR2). Specifies the defer IPG. Equal to (IPGR2+3) x 8
when DJHDX=0 and equal to (IPGR2+5) x 8 when DJHDX=1.
Reserved. Reads as 0b. Should be written to 0b for future compatibility.
®
5 Series Express Chipset MAC Programming Interface
Description